VCO Digital Sampling Oscilloscope for On-Chip Supply Noise Sensing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional circuit designs face challenges in achieving sustained area and power efficiency due to increasing peak current and current density, which require stringent power supply impedance management, especially in environments prone to resonance, making it difficult to integrate effective on-chip monitoring and characterization of voltage noise in multi-core SoC designs.
Innovation Solution
A novel all-digital digital sampling oscilloscope (OC-DSO) architecture using a voltage-controlled oscillator (VCO) with a multi-path gated structure and integrated sampling logic, implemented with FinFET standard cells, enabling scalable, high-frequency sampling while maintaining resolution and voltage range coverage, and supporting adaptive clocking schemes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If power supply impedance is reduced to minimize IR voltage drop and power loss, then power delivery efficiency is improved, but the system becomes prone to resonance at multiple frequencies
Solution Approach 1:
The patent introduces an on-chip power noise sensor as an intermediary component that detects voltage noise caused by resonance. This sensor converts the harmful resonance effects into measurable signals that can be monitored and compensated, allowing the system to maintain low power supply impedance while managing resonance through active feedback control
Solution Approach 2:
The patent implements a feedback mechanism where the power noise sensor continuously monitors voltage noise on the power supply network and provides this information to control logic. This feedback enables dynamic adjustment of power management parameters to mitigate resonance effects while maintaining efficient power delivery
2Area of stationary object
If process technology scaling continues to improve area and power efficiency, then integration density is improved, but peak current and current density increase
Solution Approach 1:
The patent places power noise sensors and monitoring circuitry directly on the chip during the manufacturing process, rather than adding them later. This preliminary integration allows the monitoring infrastructure to be built in alongside the main circuitry, enabling early detection and management of current density issues before they cause problems
Solution Approach 2:
The patent enables the chip to monitor and manage its own power noise and current density characteristics through integrated sensors and control logic. This self-service capability allows the system to automatically adjust operating parameters to maintain efficient power delivery while preventing harmful current density effects
3Use of energy by stationary object
If supply voltage is decreased to improve power efficiency, then power consumption is reduced, but voltage collapse becomes more problematic due to stagnant package inductance scaling
Solution Approach 1:
The patent replaces traditional analog voltage regulation and monitoring mechanisms with digital sampling and processing. The power noise sensor uses digital sampling techniques to detect voltage fluctuations, and control logic processes this data to manage voltage stability, enabling precise control at lower voltages without the limitations of analog approaches
4Measurement precision
If on-chip power noise sensing and monitoring is integrated to enable real-time characterization, then voltage noise detection capability is improved, but device complexity increases
Solution Approach 1:
The patent designs the power noise sensor and monitoring circuitry to perform multiple functions: detecting voltage noise, characterizing resonance frequencies, measuring current density effects, and providing feedback for power management. This multi-functionality reduces the need for separate dedicated circuits for each measurement task, thereby limiting the increase in device complexity
Solution Approach 2:
The patent combines the power noise sensing, monitoring, and control functions into an integrated on-chip system that works cooperatively with the main processor cores. By merging these functions into a unified architecture rather than separate independent systems, the patent reduces overall complexity while maintaining comprehensive voltage noise characterization capability
Data Source
AI summary
Various implementations described herein are directed to a device with a voltage-controlled oscillator that receives an enable signal, receives a reset signal, and provides internal pulse signals including one or more coarse internal pulse signals and multiple fine internal pulse signals. The device may have a coarse sampler that receives the one or more coarse internal pulse signal and provides a coarse sampled output signal. The device may have a fine sampler that receives the multiple fine internal pulse signals and provides a fine sampled output signal.