LC-Tank VCO Layout With Varactors Between Spiral Inductors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing layout of LC-tank VCOs with spiral inductors and MOS varactors separated by long wiring leads to significant parasitic inductance and capacitance, causing deviations in measured oscillation frequency from theoretical estimates due to added parasitic components.
Innovation Solution
The semiconductor device incorporates a configuration where the first and second MOS varactors are arranged between the first and second spiral inductors, reducing the length of coupling wiring and thereby minimizing parasitic inductance and capacitance, with the spiral inductors and varactors positioned closer to each other to shorten the coupling wiring length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If spiral inductors and MOS varactors are positioned apart from each other, then ease of layout and manufacturing is improved, but parasitic inductance and capacitance increase causing frequency deviation
Solution Approach 1:
The patent merges the MOS varactors into the region between the spiral inductors, combining previously separate components into a unified layout structure. This reduces the wiring length connecting inductors and varactors, thereby minimizing parasitic inductance and capacitance while maintaining manufacturing feasibility through systematic placement rules.
Solution Approach 2:
The patent utilizes the spatial dimension between the spiral inductors to position the MOS varactors, effectively using the area between existing components rather than extending wiring outward. This dimensional utilization reduces coupling wire length without increasing overall device footprint, addressing both frequency accuracy and layout efficiency.
2Measurement precision
If wiring length between spiral inductors and MOS varactors is reduced, then parasitic inductance and capacitance decrease improving frequency accuracy, but layout complexity increases
Solution Approach 1:
The patent applies local quality by specifically positioning MOS varactors in the region between spiral inductors where space is available, rather than using a uniform distribution approach. This localized placement strategy reduces parasitic effects in critical areas while maintaining overall layout simplicity through rule-based positioning.
Solution Approach 2:
The patent segments the VCO into distinct functional regions: spiral inductors positioned at opposite corners, MOS varactors in the intermediate region, and differential pairs in remaining areas. This segmentation allows each component type to be optimized independently while maintaining compact overall dimensions and reducing inter-component wiring.
Data Source
AI summary
A semiconductor device is provided which can reduce a parasitic inductor and/or parasitic capacitance added to the wiring that couples spiral inductors and MOS varactors included in a VCO. An LC-tank VCO includes first and second spiral inductors, and first and second MOS varactors. As seen perpendicularly to the semiconductor substrate, the first and second MOS varactors are arranged in a region between the first spiral inductor and the second spiral inductor.