VCSEL Air Gap Optical Confinement Wafer Bonding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The design and fabrication of long wavelength VCSELs face challenges in performance, reliability, and cost, particularly due to high thermal resistance and manufacturing costs associated with dielectric DBRs, and the sensitivity of wafer fusion processes to surface morphology and thermal expansion mismatches between GaAs and InP substrates.
Innovation Solution
The proposed solution involves bonding InP-based MQLs with a buried TJ active material to a GaAs-based DBR bottom mirror reflector, using dielectric materials for the top DBR reflector, and introducing air gaps for enhanced optical confinement, while reversing the wafer bonding and TJ regrowth sequence to reduce dimensional scaling and improve surface morphology, thereby optimizing the VCSEL structure for single-mode and multi-mode operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If wafer fused GaAs based DBRs and InP based active region are used, then thermal management is improved, but manufacturing cost increases due to sacrifice of substrates and epitaxial growth
Solution Approach 1:
The VCSEL structure is divided into two separately fabricated wafers (GaAs-based DBR wafer and InP-based active region wafer) that are subsequently bonded together. This segmentation allows each wafer to be optimized independently for its specific function while enabling cost-effective manufacturing through separate processing streams.
Solution Approach 2:
A bonding interface is introduced as an intermediary between the GaAs-based DBR and InP-based active region. This bonding interface enables thermal management benefits of wafer fusion while avoiding the need to sacrifice entire substrates, as the bonding process can be optimized to minimize material loss.
2Temperature
If wafer fusion process is used, then thermal management is improved, but manufacturing complexity increases due to sensitivity to surface morphology
Solution Approach 1:
Surface preparation and morphology optimization are performed as preliminary actions before the wafer bonding process. The GaAs and InP wafers are separately processed to achieve optimal surface conditions, which simplifies the subsequent bonding process and reduces sensitivity to morphology variations during fusion.
3Strength
If high temperature wafer fusion is used, then bonding strength is improved, but dimensional accuracy deteriorates due to thermal expansion mismatch
Solution Approach 1:
The bonding process parameters are optimized to achieve sufficient bonding strength at reduced temperatures. By adjusting bonding pressure, time, and temperature parameters, the process achieves adequate bonding strength while minimizing thermal expansion mismatch between GaAs and InP materials, thereby preserving dimensional accuracy.
4Ease of manufacture
If dielectric DBRs are used, then manufacturing cost is reduced, but thermal resistance increases
Solution Approach 1:
Different materials with different thermal properties are used in different locations of the VCSEL structure. Dielectric DBRs are used where cost reduction is prioritized, while metal layers and GaAs-based structures are positioned in regions where thermal management is critical, achieving local optimization of both cost and thermal performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the performance and reliability of VCSELs by reducing thermal resistance, lowering manufacturing costs, and improving the yield of the wafer bonding process, while allowing for more flexible engineering of the regrowth processes and increased optical confinement, thus achieving comparable metrics to short wavelength VCSEL technology at a lower cost.
Implementation Method 1
a first reflector disposed on the first substrate, wherein the first reflector comprises a distributed Bragg reflector (DBR) including multiple layers of alternating semiconductor materials; a second reflector, wherein the second reflector comprises a distributed Bragg reflector (DBR) including multiple alternating dielectric layers
Implementation Method 2
bonding InP-based MQLs with a buried TJ active material to a GaAs-based DBR bottom mirror reflector
Implementation Method 3
introducing air gaps for enhanced optical confinement
Data Source
AI summary
Several VCSEL devices for long wavelength applications in wavelength range of 1200-1600 nm are described. These devices include an active region between a semiconductor DBR on a GaAs wafer and a dielectric DBR regrown on the active region. The active region includes multi-quantum layers (MQLs) confined between the active n-InP and p-InAlAs layers and a tunnel junction layer above the MQLs. The semiconductor DBR is fused to the bottom of the active region by a wafer bonding process. The design simplifies integrating the reflectors and the active region stack by having only one wafer bonding followed by regrowth of the other layers including the dielectric DBR. An air gap is fabricated either in an n-InP layer of the active region or in an air gap spacer layer on top of the semiconductor DBR. The air gap enhances optical confinement of the VCSEL. The air gap may also contain a grating.