VCSEL Array Layout Asymmetry for Defect Mitigation
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Solution Overview
Problem
Conventional VCSEL arrays are prone to emitter failures due to crystallographic defects, which can lead to significant power output degradation and array failure when extended defects align with the emitter layout, impacting multiple emitters and devices.
Innovation Solution
The VCSEL array layout is intentionally mis-aligned with respect to the xy-plane of the semiconductor material's crystallographic axes by skewing or rotating the emitter array, reducing the probability of extended defects affecting a large number of emitters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the VCSEL array is aligned with the xy-plane of the crystallographic axes, then the manufacturing and measurement are simplified, but the probability of extended defects impacting multiple emitters increases significantly
Solution Approach 1:
The patent applies asymmetry by deliberately misaligning the VCSEL array layout with respect to the crystallographic xy-plane. The array is rotated or skewed at specific angles (e.g., 15-75 degrees) relative to the crystallographic axes, breaking the symmetric alignment that would otherwise simplify manufacturing. This asymmetric positioning reduces the probability that extended defects along crystallographic planes will intersect multiple emitters, thereby improving reliability while accepting increased manufacturing complexity.
Solution Approach 2:
The patent introduces a rotational dimension to the array layout problem. Instead of only considering the two-dimensional grid positioning of VCSELs, the solution adds a third dimensional parameter: the rotation angle of the entire array relative to the crystallographic axes. This dimensional change allows the system to optimize for defect avoidance by selecting specific angular orientations that minimize defect-emitter intersections.
2Reliability
If the emitter array is mis-aligned with the crystallographic xy-plane, then the probability of extended defects affecting emitters is reduced, but the manufacturing precision and alignment complexity increase
Solution Approach 1:
The patent changes the geometric parameters of the array layout by introducing specific rotation angles (e.g., 15, 30, 45, 60, or 75 degrees) relative to the crystallographic axes. This parameter change transforms the alignment problem from a simple axis-aligned configuration to an angled configuration that statistically reduces defect impact. The specific angle selection optimizes the balance between reliability improvement and manufacturing complexity.
3Ease of manufacture
If a regular grid pattern is used for VCSEL arrangement, then the manufacturing process is simplified, but extended defects can impact large numbers of emitters along crystallographic planes
Solution Approach 1:
The patent breaks the symmetric regular grid pattern by rotating the entire array at an angle relative to the crystallographic axes. This asymmetric transformation maintains the regular spacing between emitters (facilitating manufacturing) while changing the orientation so that extended defects along crystallographic planes are less likely to pass through multiple emitters in the array.
Data Source
AI summary
An array layout of VCSELs is intentionally mis-aligned with respect to the xy-plane of the device structure as defined by the crystallographic axes of the semiconductor material. The mis-alignment may take the form of skewing the emitter array with respect to the xy-plane, or rotating the emitter array. In either case, the layout pattern retains the desired, row/column structure (necessary for dicing the structure into one-dimensional arrays) while reducing the probability that an extended defect along a crystallographic plane will impact a large number of individual emitters.