Symmetrical VCSEL Array Layout for Low Pulse Delay
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Solution Overview
Problem
Existing VCSEL arrays suffer from variations in impedance along different current paths, leading to delays in optical pulses and reduced precision in time-of-flight measurements.
Innovation Solution
The VCSEL array design ensures symmetrical current paths by arranging VCSEL sub-arrays on a common substrate with symmetric electrical contact arrangements, minimizing impedance differences and pulse delays, and using a flip-chip configuration with bumps for electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If VCSEL sub-arrays are electrically connected in series on a common substrate, then device integration is improved, but impedance variations along current paths increase causing pulse delays
Solution Approach 1:
The patent applies asymmetry by intentionally designing the electrical contact arrangement to compensate for the inherent asymmetry in current path lengths. By strategically positioning contact pads and routing traces, the design creates an asymmetric compensation scheme that balances the total impedance across all VCSEL sub-arrays, thereby reducing pulse delays while maintaining high device integration
2Ease of manufacture
If current paths are made asymmetric to simplify manufacturing, then ease of manufacture is improved, but impedance variations increase causing optical pulse delays
Solution Approach 1:
The patent implements equipotentiality by designing the electrical contact arrangement to equalize the impedance potential across all VCSEL sub-arrays. Through careful selection of contact pad positions and trace geometries, the design ensures that all current paths experience approximately equal impedance, creating an equipotential condition that synchronizes optical pulse emission while maintaining manufacturing simplicity
Data Source
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AI summary
The invention describes a Vertical Cavity Surface Emitting Laser (VCSEL) array (100) comprising at least two VCSEL sub-arrays, wherein each VCSEL sub-array comprises a multitude of VCSELs arranged on a substrate (110), wherein the at least two VCSEL sub-arrays are electrically contacted by means of a first electrical contact arrangement (105, 107) common to the VCSELs within a respective VCSEL sub-array, and a second electrical contact arrangement (150, 155), wherein the second electrical contact arrangement (150, 155) comprises a multitude of second electrical contacts (150), each second electrical contact (150) contacting a respective single VCSEL within the respective VCSEL sub-array individually, wherein each second electrical contact (150) comprises a second metal- semiconductor interface to a second semiconductor layer of an associated VCSEL of the multitude of VCSELs, wherein the second electrical contacts (150) are arranged to electrically pump the associated VCSEL along a current path to the first electrical contact arrangement (105, 107), wherein the current paths between the first electrical contact arrangement (105, 107) and the second electrical contacts (150) via the multitude of VCSELs are characterized by at least one symmetry selected out of the group of rotation symmetry, mirror symmetry and translation symmetry. The invention further relates to a light emitting device comprising such a VCSEL array (100), a time of flight camera comprising such a light emitting device or VCSEL array (100) and a method of manufacturing the VCSEL array (100).