VCSEL Array RDL Layout for Intermixed Emitters and Low Capacitance
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Solution Overview
Problem
Existing VCSEL arrays with intermixed and irregular emitter locations face complications in design and processing, including capacitance issues, emitter power uniformity, and dielectric breakdown, particularly in multi-channel configurations.
Innovation Solution
The use of a bottom RDL with alternating row contacts and multi-layer redistribution layers to connect emitters, minimizing the number of RDLs required and simplifying the design and fabrication process, while ensuring effective isolation between channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If vertically stacked sheet contacts are used to enable intermixed and irregular emitter locations, then emitter positioning flexibility is improved, but device complexity and processing difficulty increase
Solution Approach 1:
The patent divides the VCSEL array into multiple independent channels with separate address layers. Each address layer controls a specific subset of VCSELs, allowing irregular and intermixed emitter locations while maintaining simplified processing for each channel. The segmentation of control signals and address layers reduces the overall processing complexity despite the irregular layout.
Solution Approach 2:
The patent transitions from planar emitter arrangements to vertically stacked sheet contacts in the third dimension. This vertical stacking allows emitters to be positioned at irregular locations and intermixed across different channels without increasing lateral processing complexity, as the connections are established through vertical vias and stacked conductive layers.
2Adaptability or versatility
If vertically stacked sheet contacts are used for irregular emitter locations, then emitter intermixing capability is improved, but capacitance between contacts increases
Solution Approach 1:
The patent extracts and eliminates the vertically stacked sheet contact structure that caused excessive capacitance. Instead, it uses laterally separated address layers with selective via connections to achieve emitter intermixing. This removes the harmful capacitive coupling between vertically stacked contacts while preserving the ability to address irregularly positioned emitters.
Solution Approach 2:
The patent introduces intermediate via structures that selectively connect address layers to specific VCSEL groups. These intermediaries allow controlled signal routing to intermixed emitters without requiring direct vertical stacking of sheet contacts, thereby reducing capacitance while maintaining intermixing capability.
3Adaptability or versatility
If vertically stacked sheet contacts are used to achieve irregular emitter locations, then emitter power uniformity deteriorates due to different series resistances
Solution Approach 1:
The patent segments the array into multiple channels with dedicated address layers, where each channel controls a specific group of VCSELs. This segmentation allows independent optimization of the electrical path for each channel, ensuring uniform power distribution to irregularly located emitters within each channel while maintaining the ability to address different channels independently.
Solution Approach 2:
The patent applies local quality by designing channel-specific address layers and via structures tailored to the local distribution of VCSELs in each channel. This allows optimization of series resistance and power uniformity for each local group of emitters, rather than using a uniform approach that would fail to accommodate irregular locations.
4Ease of manufacture
If multi-layer redistribution layers are used to connect emitters in intermixed channels, then design simplicity is improved, but number of RDLs required increases
Solution Approach 1:
The patent segments the redistribution function into channel-specific address layers rather than using a monolithic multi-layer RDL structure. Each address layer handles a specific channel, reducing the need for numerous overlapping RDL layers while maintaining the ability to connect intermixed emitters across different channels through selective via structures.
Data Source
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AI summary
This disclosure describes a device having a plurality vertical cavity surface emitting lasers (VCSELs) that are addressable in groups. The device has a bottom RDL that is able to electrically couple a first group of VCSELs to a first bond pad through to a bond pad via. The device also has a top RDL that is able to electrically couple a second group of VCSELs to a second bond pad through a group of VCSEL vias. Each VCSEL of the second group of VCSELs is electrically coupled to a corresponding VCSEL via of the group of VCSEL vias. Furthermore, the plurality of VCSEL may be positioned in any manner including randomly.