VCSEL Packaging Flatness Control via Differential Pressure
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Solution Overview
Problem
Packaging large size VCSEL arrays is challenging due to difficulties in maintaining chip flatness, especially for thin or ultra-thin chips that tend to warp, requiring different pressures across the chip surface during the packaging process.
Innovation Solution
A method involving pre-testing the VCSEL chip for optical flatness using low power laser illumination and applying differential pressure to flatten the chip before packaging, followed by flux-less soldering in a controlled environment, such as vacuum or inert atmosphere, to ensure proper alignment and bonding to submounts or printed circuit boards.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If thin or ultra-thin VCSEL chips are used, then heat dissipation is improved, but chip flatness deteriorates causing warping
Solution Approach 1:
The patent applies preliminary action by testing VCSEL chip flatness before packaging and applying differential pressure to flatten the chip in advance. This pre-correction of warping ensures proper alignment and bonding during subsequent packaging processes, resolving the contradiction between using thin chips for heat dissipation and maintaining chip flatness.
2Strength
If conventional soldering with flux is used, then bonding strength is improved, but oxidation and air voids occur
Solution Approach 1:
The patent employs inert atmosphere by performing soldering in a controlled environment such as vacuum or inert gas atmosphere. This eliminates oxygen contact during bonding, preventing oxidation and air void formation while maintaining strong bonding, thus resolving the contradiction between bonding strength and harmful factors.
3Ease of manufacture
If uniform pressure is applied during packaging, then process simplicity is improved, but alignment precision deteriorates for warped chips
Solution Approach 1:
The patent applies local quality by implementing differential pressure application across different regions of the VCSEL chip surface. Instead of uniform pressure, specific areas receive different pressure levels to locally correct warping and achieve proper flatness and alignment, resolving the contradiction between process simplicity and alignment precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures efficient heat dissipation and thermal/electrical performance by maintaining chip flatness and avoiding air voids or oxidation, enhancing the reliability and efficiency of VCSEL arrays in high-power optical modules.
Implementation Method 1
pre-testing the VCSEL chip for optical flatness using low power laser illumination
Implementation Method 2
flux-less soldering in a controlled environment, such as vacuum or inert atmosphere, to ensure proper alignment and bonding
Data Source
AI summary
A process to bond VCSEL arrays to submounts and printed circuit boards is provided. The process is particularly suited to large area thin and ultra-thin VCSEL arrays susceptible to bending and warping. The process integrates a flatness measurement step and applying appropriate combination of pressure prior to bonding the VCSEL array to the submount or a printed circuit using a vacuum flux-less bonding process. The process is very promising in making very good quality bonding between the VCSEL array and a submount or a printed circuit board. The process is applied to construct optical modules with improved flatness that may be integrated with other electronic components in constructing optoelectronic systems.