VCSEL Planarization and Via Routing for Smaller Footprints
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Solution Overview
Problem
Conventional VCSEL fabrication methods result in devices with a large footprint due to the need for bonding areas and metal tracks that overcome surface topologies, making them mechanically unstable and requiring significant space, which is not efficient for advanced routing concepts.
Innovation Solution
A method involving the application of cover materials to planarize the non-planar VCSEL structure, followed by the creation of electrical vias for direct electrical connections, reducing the device footprint and enabling more efficient electrical routing within the chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional VCSEL fabrication methods are used with bonding areas and metal tracks to overcome surface topologies, then electrical connections can be established, but the device footprint becomes large (3/4 of footprint for bonding areas and support structures)
Solution Approach 1:
The patent applies planarization technology to transform the three-dimensional non-planar surface topology into a two-dimensional planar surface. By filling the valleys and removing peaks through chemical mechanical polishing or etch-back processes, the surface is flattened to enable direct electrical connections without requiring metal tracks to overcome altitude differences, thereby reducing the footprint from 3/4 bonding areas down to minimal bonding areas.
Solution Approach 2:
The invention extracts and eliminates the intermediate metal track structures and large bonding areas from the conventional VCSEL fabrication process. By directly connecting the VCSEL contact areas after planarization, the patent removes the unnecessary intermediate connection layers, reducing both the footprint and structural complexity while maintaining electrical connectivity.
2Reliability
If multiple etching steps are performed to create topologies for electrical isolation, then VCSELs are electrically isolated, but the surface topology becomes non-planar with altitudes up to 15 μm
Solution Approach 1:
The patent performs planarization as a preliminary action before applying bonding materials and forming final electrical connections. By flattening the surface early in the fabrication process, subsequent steps can proceed on a planar surface, eliminating the need for complex graded etching profiles and specialized deposition processes that would be required to accommodate non-planar topologies.
Solution Approach 2:
Instead of adapting the bonding and connection process to accommodate the non-planar surface topology created by etching, the patent inverts the approach by first planarizing the surface and then performing standard bonding and connection steps on the flattened surface, thereby simplifying the overall fabrication process.
3Ease of manufacture
If direct soldering is attempted on the VCSEL structure, then electrical contact can be made, but the VCSEL is mechanically unstable due to previous oxidation processes
Solution Approach 1:
The patent introduces planarization as an intermediary process step between the oxidation process and the soldering process. This intermediate planarization step not only flattens the surface for proper soldering but also stabilizes the VCSEL structure by providing a solid, flat foundation that compensates for the mechanical instability caused by previous oxidation processes, enabling reliable direct soldering.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method results in VCSEL devices with a significantly reduced footprint, improved mechanical stability, and allows for more efficient electrical connections and heat transfer, facilitating the integration of photonic components and enabling densely packed VCSEL arrays.
Implementation Method 1
applying one or more layers of cover material different from the one or more semiconductor materials on the non-planar first structure top surface
Implementation Method 2
planarizing the second structure top surface
Data Source
AI summary
A method of fabricating a Vertical Cavity Surface Emitting Laser(VCSEL) device includes providing a first structure comprising a VCSEL layer structure on a wafer. The first structure has a non-planar first structure top surface with varying height levels and includes one or more electrical contact areas. The method further includes applying one or more layers of cover material on the non-planar first structure top surface with a thickness such that a lowest height level of a cover material top surface is equal to or above the highest height level of the non-planar first structure top surface, to obtain a second structure having a second structure top surface, planarizing the second structure top surface, and producing one or more first electrical vias from the second structure top surface through the one or more layers of cover material for electrical connection to the one or more electrical contact areas.