VCSEL Electrode Layout Using Sidewall Conduction Without Wire Bonding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing VCSEL devices require a wire bonding process to connect the positive electrode to the substrate, which increases the device size and reduces layout density.
Innovation Solution
The VCSEL device design places the positive and negative electrodes on the same surface of the epitaxial layer, with the positive electrode connected to the ohmic contact layer through a conductive layer on the sidewall, eliminating the need for wire bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding is used to connect the positive electrode to the substrate, then electrical connection is achieved, but the device size increases and layout density decreases
Solution Approach 1:
The patent merges the positive electrode connection function with the device body structure by integrating the conductive layer directly into the sidewall of the epitaxial layer. This eliminates the need for separate wire bonding components and reduces the overall device footprint while maintaining reliable electrical connection between the positive electrode and substrate.
Solution Approach 2:
The patent transitions from a planar wire bonding approach to a three-dimensional conductive path by forming the conductive layer on the sidewall surface of the epitaxial layer. This vertical integration utilizes the third dimension (height/depth) to achieve electrical connection, thereby reducing the horizontal area required for bonding pads and wires.
2Reliability
If wire bonding is used to connect the positive electrode to the substrate, then electrical connection is achieved, but the layout density of the device body on the substrate decreases
Solution Approach 1:
The patent combines the electrical connection function with the device body structure itself by forming the conductive layer as an integral part of the sidewall. This eliminates the need for separate wire bonding processes and bonding pad areas, thereby increasing the layout density of functional device bodies that can be packed on the substrate.
Solution Approach 2:
The patent extracts the wire bonding process and bonding pad requirements from the device structure. By eliminating these separate components and their associated process steps, the design achieves higher layout density while maintaining reliable electrical connection through the integrated conductive layer.
3Reliability
If wire bonding process is used, then positive electrode connection is achieved, but manufacturing complexity and process steps increase
Solution Approach 1:
The patent merges the electrical connection function into the device fabrication process itself by forming the conductive layer during epitaxial growth or subsequent deposition steps. This integration eliminates the need for separate wire bonding manufacturing steps, reducing overall process complexity while ensuring reliable electrical connection.
Solution Approach 2:
The conductive layer is formed in advance during the device fabrication process, before final assembly. This preliminary formation of the conductive path on the sidewall eliminates the need for subsequent wire bonding operations, simplifying the manufacturing process while guaranteeing electrical connection reliability.
Data Source
AI summary
A vertical cavity surface emitting laser (VCSEL) device and a method for manufacturing the VCSEL device without wire bonding process for the topmost positive electrode are disclosed. The device includes epitaxial layer, ohmic contact layer, positive electrode, first insulating layer, conductive layer, and negative electrode. The epitaxial layer includes first and second opposing surfaces, and sidewalls connected to first and second surfaces. The ohmic contact layer is disposed on the first surface and the positive electrode connected thereto is disposed on the second surface. The first insulating layer is disposed on the second surface and extends to the ohmic contact layer along the sidewall. The conductive layer is disposed on the first insulating layer corresponding to the sidewall/sidewalls which carry power for the positive electrode.