VCXO PLL Clock Synchronization for MPEG2-TS Timestamp Accuracy
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Solution Overview
Problem
Conventional recording/output apparatuses for MPEG2-TS fail to accurately reproduce transport packet intervals during playback, leading to system clock deviations that cause buffer overflows/underflows and image issues due to the use of low-frequency stability crystal oscillators, which do not meet the required accuracy for proper decoding and display.
Innovation Solution
A digital broadcast receiver with a clock reproduction section that synchronizes the system clock with the broadcast station's encoding/multiplexing clock, using a VCXO and PLL configuration to generate a highly accurate receiver system clock, and a timestamp addition section that embeds timestamps into transport packets to ensure accurate packet interval reproduction during recording and playback.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a crystal oscillator is used for the time counter clock, then the device complexity is reduced, but the system clock accuracy deteriorates below the required 27 MHz±30 ppm
Solution Approach 1:
The patent introduces a PLL (Phase Lock Loop) circuit as an intermediary between the crystal oscillator and the system clock. The PLL multiplies the crystal oscillator frequency to achieve the required 27 MHz system clock accuracy of ±30 ppm, while keeping the crystal oscillator itself simpler and less expensive.
Solution Approach 2:
The patent changes the frequency parameter by using a PLL to multiply the crystal oscillator frequency. This allows the system to achieve the required 27 MHz±30 ppm accuracy through frequency multiplication and phase locking, rather than relying solely on the crystal oscillator's native frequency stability.
2Device complexity
If the system clock accuracy is below 27 MHz±30 ppm, then the device complexity is reduced, but buffer overflows and underflows occur causing image degradation
Solution Approach 1:
The patent implements a feedback mechanism using the PLL circuit that continuously monitors and adjusts the system clock phase and frequency. This feedback ensures the clock remains within ±30 ppm accuracy, preventing STD buffer overflows and underflows that would cause image degradation.
Solution Approach 2:
The patent uses the accurate PLL-synchronized clock to prevent buffer overflows and underflows before they occur. By maintaining precise clock accuracy ahead of time, the system avoids the harmful effects of buffer errors on image quality.
3Ease of manufacture
If a simple crystal oscillator is used, then the manufacturing cost is reduced, but the transport packet interval reproduction accuracy deteriorates
Solution Approach 1:
The patent introduces a PLL circuit as an intermediary that allows the use of a simpler, less expensive crystal oscillator while still achieving the required packet interval accuracy. The PLL compensates for the crystal oscillator's lower native accuracy through frequency multiplication and phase locking.
Solution Approach 2:
The patent changes the frequency and phase parameters through PLL processing, allowing a cost-effective crystal oscillator to produce the required 27 MHz±30 ppm system clock accuracy for proper MPEG2-TS packet interval reproduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution ensures that recorded and played transport packet intervals align with reception timing, maintaining system clock accuracy within the permissible range, preventing buffer issues and ensuring proper image reproduction and decoding.
Implementation Method 1
a clock reproduction section that reproduces a receiver system clock synchronized (for frequency/phase matching) with the system clock of a broadcast station's encoding/multiplexing section
Implementation Method 2
using a VCXO and PLL configuration to generate a highly accurate receiver system clock
Data Source
AI summary
Formerly, it was difficult to exercise proper control for recording and outputting a plurality of contiguous data. To solve this problem, for example, a plurality of contiguous data are acquired from a stream in which the reference information for reproducing at an acquisition end a clock synchronized with a system clock prevailing at the time of generation is multiplexed. A plurality of timestamped data are then read from recording means. Timestamp information is removed from the read timestamped information. The resulting data without the timestamp information is handled as the read data and output with the timing dependent on the timestamp information. The timestamp information generation operation performed for a write and the output operation performed for a read with the timing dependent on the timestamp information are synchronized with an adjusted clock.