Variable Delay Line Entry-Point Voltage Scaling in DLLs
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Solution Overview
Problem
Existing variable delay line (VDL) architectures in delay locked loops (DLLs) face challenges in providing stable and flexible delay control across a wide range of frequencies and temperatures, often requiring numerous stages and buffer stages, which increase layout size and power consumption, and are sensitive to power supply variations.
Innovation Solution
The VDL power supply voltage, VccVDL, is regulated based on the entry point into the delay line, with higher voltages for smaller delays and lower voltages for larger delays, allowing for graduated delays without separate stage design and potentially eliminating the need for buffer stages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the VDL uses numerous stages and buffer stages to provide stable delay control across wide frequency and temperature ranges, then the delay control stability and frequency range are improved, but the layout size and power consumption increase
Solution Approach 1:
The patent changes the power supply voltage parameter of the VDL dynamically based on the entry point position. When the entry point is at earlier stages (providing larger delay), a lower voltage is applied to reduce power consumption. When the entry point is at later stages (providing smaller delay), a higher voltage is applied to maintain timing accuracy. This voltage scaling approach allows the VDL to operate across a wide frequency range while significantly reducing power consumption compared to operating at maximum voltage always.
2Reliability
If the VDL uses numerous stages and buffer stages to provide stable delay control, then the delay control stability is improved, but the layout size increases
Solution Approach 1:
The patent uses voltage scaling as a function of entry point position to extend the effective delay range of each stage. By applying lower voltages at earlier stages and higher voltages at later stages, the same physical stages can provide both large and small delay values with appropriate precision, eliminating the need for additional buffer stages and reducing the overall layout area while maintaining delay control stability.
3Measurement precision
If the VDL operates at higher power supply voltage, then the delay precision and timing accuracy are improved, but the power consumption increases
Solution Approach 1:
The patent implements dynamic voltage scaling where the power supply voltage to the VDL is adjusted based on the entry point position. When the entry point is at later stages where smaller delay precision is needed, a lower voltage is applied, reducing power consumption. When the entry point is at earlier stages where larger delay precision is critical for timing alignment, a higher voltage is applied to maintain accuracy. This selective voltage application optimizes the trade-off between delay precision and power consumption across different operating conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables a VDL/DLL design that operates over a wider frequency range with reduced stages and power consumption, providing flexible and stable delay control with reduced sensitivity to power supply variations and eliminating the need for buffer stages.
Implementation Method 1
the voltage regulator is modified to modify the power supply to the variable delay line as a function of the entry point
Data Source
AI summary
Disclosed herein is a VDL/DLL architecture in which the power supply to the VDL, VccVDL, is regulated at least as a function of the entry point of the input signal (ClkIn) into the VDL. Specifically, VccVDL is regulated to be higher when the delay through the VDL is relatively small (when the entry point is toward the right (or minimum delay) edge of the VDL) and is reduced when the delay is relatively high (when the entry point is toward the left (or maximum delay) edge of the VDL). This provides for graduated delays across the stages of the VDL, but without the need to design each stage separately. Other benefits include a VDL/DLL design operable over a wider range of frequencies, and a reduced number of stages, including a reduced number of buffer stages. Moreover, when the disclosed technique is used, buffer stages may be dispensed with altogether. Additionally, the disclosed VDL architecture can be used in any situation where it might be advantageous to delay a signal through a variable delay as a function of VDL entry point.