Variable Delay Line Entry-Point Voltage Control for Fewer Stages
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Solution Overview
Problem
Existing variable delay line (VDL) architectures in integrated circuits face challenges in providing stable and flexible delay control over a wide range of frequencies and temperatures, often requiring a large number of stages and being sensitive to power supply variations, which complicates the circuitry and increases layout and power consumption.
Innovation Solution
The VDL power supply voltage, VccVDL, is regulated based on the entry point into the delay line, with higher voltages applied for smaller delays and lower voltages for larger delays, allowing for graduated delays across stages without the need for physical differences in transistor properties, thereby reducing the number of stages and eliminating the need for buffer stages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a large number of stages are used in the VDL to provide stable delay control over a wide frequency range, then the delay control stability and frequency range are improved, but the layout area and power consumption increase
Solution Approach 1:
The patent changes the operating voltage parameter of the VDL dynamically. By adjusting the voltage supplied to the delay line stages based on the current delay setting, the patent achieves graduated delay values without requiring physically different transistor configurations. Higher voltages enable smaller delays while lower voltages enable larger delays, allowing a compact design to cover a wide frequency range.
Solution Approach 2:
The patent introduces dynamic voltage adjustment to the VDL stages. Instead of using static transistor properties to determine delay values, the system dynamically changes the supply voltage to each stage based on the desired delay setting. This dynamic approach allows the same physical hardware to provide multiple delay values, reducing the number of stages needed.
2Measurement precision
If physically different transistor properties are used across VDL stages to achieve graduated delays, then the delay resolution is improved, but the manufacturing complexity and layout difficulty increase
Solution Approach 1:
Instead of manufacturing transistors with different physical properties across stages, the patent changes the operating voltage parameter to achieve graduated delays. All transistors can be identical in structure and size, but they operate at different voltages depending on their position in the delay line, providing the needed delay variation without manufacturing complexity.
Solution Approach 2:
The patent uses homogeneous transistor structures throughout the VDL. All delay stages use the same transistor design, layout, and manufacturing parameters. The differentiation between stages is achieved through voltage control rather than physical differences, simplifying both manufacturing and design.
3Device complexity
If the VDL is sensitive to power supply variations to achieve simpler circuitry, then the circuit complexity is reduced, but the delay stability and reliability worsen
Solution Approach 1:
The patent implements a feedback mechanism where the voltage regulator monitors the delay line operation and adjusts the supply voltage accordingly. Based on the current entry point or delay setting, the regulator provides the appropriate voltage to maintain stable delay characteristics. This feedback loop compensates for power supply variations and ensures reliable operation.
Solution Approach 2:
The patent introduces a voltage regulator as an intermediary between the power supply and the VDL stages. This intermediary component isolates the delay line from direct power supply variations and provides a stabilized, controlled voltage. The regulator acts as a buffer that protects the VDL from supply noise while enabling precise delay control.
4Adaptability or versatility
If buffer stages are added to the VDL to extend the delay range, then the frequency range is improved, but the layout area and power consumption increase
Solution Approach 1:
The patent uses voltage parameter changes to extend the delay range instead of adding buffer stages. By adjusting the voltage to existing VDL stages, the system can achieve both small and large delay values, effectively covering a wide frequency range without requiring additional buffer hardware, thus avoiding the associated power consumption and area overhead.
Data Source
AI summary
Disclosed herein is a VDL/DLL architecture in which the power supply to the VDL, VccVDL, is regulated at least as a function of the entry point of the input signal (ClkIn) into the VDL. Specifically, VccVDL is regulated to be higher when the delay through the VDL is relatively small (when the entry point is toward the right (or minimum delay) edge of the VDL) and is reduced when the delay is relatively high (when the entry point is toward the left (or maximum delay) edge of the VDL). This provides for graduated delays across the stages of the VDL, but without the need to design each stage separately. Other benefits include a VDL/DLL design operable over a wider range of frequencies, and a reduced number of stages, including a reduced number of buffer stages. Moreover, when the disclosed technique is used, buffer stages may be dispensed with altogether. Additionally, the disclosed VDL architecture can be used in any situation where it might be advantageous to delay a signal through a variable delay as a function of VDL entry point.