Auto-Aligned VDMOS Source Layout for Parasitic BJT Suppression
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Solution Overview
Problem
Existing power MOSFET devices face malfunctions due to the activation of parasitic bipolar transistors during unclamped inductive switching, leading to voltage drops that can cause faults, especially when high currents are involved.
Innovation Solution
A method for manufacturing a MOS transistor that includes forming a body region with a second conductivity type, a source region, a drain electrode, and a gate electrode, along with structural regions and spacers that are auto-aligned to minimize electrical resistance and prevent parasitic bipolar transistor activation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If voltage clamp circuits are used to limit voltage drop, then parasitic bipolar transistor activation is prevented, but device complexity and cost increase
Solution Approach 1:
The patent extracts the voltage limiting function from external voltage clamp circuits and implements it directly within the semiconductor device structure through the P-type body region and N+ source region configuration, eliminating the need for separate voltage clamp circuits while maintaining protection against parasitic bipolar transistor activation
Solution Approach 2:
The P-type body region acts as an intermediary element between the N-type substrate and N+ source region, providing a controlled path for current flow that limits voltage drop and prevents parasitic bipolar transistor activation without requiring external protection circuits
2Productivity
If unclamped inductive switching occurs, then high current handling is achieved, but voltage drop activates parasitic bipolar transistor causing faults
Solution Approach 1:
The patent changes the electrical parameters of the device by introducing a P-type body region with specific doping concentration between the N-type substrate and N+ source region, which modifies the voltage characteristics and current flow path to prevent parasitic bipolar transistor activation during high current switching operations
3Ease of manufacture
If source electrode is not auto-aligned with gate electrode, then manufacturing is simpler, but asymmetry increases electrical resistance
Solution Approach 1:
The manufacturing process uses the gate electrode structure itself as a self-aligning reference for the source electrode formation, where the source electrode is automatically positioned relative to the gate electrode through the etching and deposition processes, ensuring symmetry without requiring complex external alignment procedures
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The auto-aligned manufacturing process reduces the electrical resistance in the body region, minimizing the potential drop between the base and emitter of the parasitic bipolar transistor, thereby preventing malfunctions and allowing for increased current handling under unclamped inductive switching conditions.
Implementation Method 1
forming at said step one or more spacers by performing an unmasked anisotropic etching of said structural layer with a main etching direction parallel to the axis of symmetry
Data Source
AI summary
A MOS transistor, in particular a vertical channel transistor, includes a semiconductor body housing a body region, a source region, a drain electrode and gate electrodes. The gate electrodes extend in corresponding recesses which are symmetrical with respect to an axis of symmetry of the semiconductor body. The transistor also has spacers which are also symmetrical with respect to the axis of symmetry. A source electrode extends in electrical contact with the source region at a surface portion of the semiconductor body surrounded by the spacers and is in particular adjacent to the spacers. During manufacture the spacers are used to form in an auto-aligning way the source electrode which is symmetrical with respect to the axis of symmetry and equidistant from the gate electrodes.