VDMOS Split-Gate Trench Structure for Lithography Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing VDMOS manufacturing processes require additional polysilicon lithography layers for split-gate technology, increasing processing costs and complicating subsequent photolithography and etching processes due to the need for separate leading-out of gate electrodes.
Innovation Solution
A method for manufacturing VDMOS devices that allows separate leading-out of first and second electrodes without increasing polysilicon lithography layers, where all polysilicon gates remain in the trench, eliminating surface steps and simplifying subsequent processes by forming specific trench regions and using insulating layers to control polysilicon layer placement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If split-gate technology with dual gate design is used, then gate control capability is improved, but polysilicon lithography complexity increases
Solution Approach 1:
The patent divides the single gate structure into two separate gates: a first gate and a second gate. The first gate extends from the active region toward the drift region, while the second gate is positioned in the drift region. This segmentation allows independent control of different regions, improving gate control capability without requiring complex polysilicon lithography processes, as each gate can be formed using standard lithography steps.
Solution Approach 2:
The patent positions the two gates at different spatial locations and orientations within the device structure. The first gate has a specific extension direction from the active region, while the second gate is positioned in the drift region, creating a three-dimensional gate configuration. This dimensional arrangement enables enhanced control over charge distribution and electric field without increasing lithography complexity.
2Ease of operation
If additional polysilicon lithography layers are added for separate gate leading-out, then gate electrode separation is achieved, but processing costs increase
Solution Approach 1:
The patent combines the formation of the first and second gates into a unified structure where both gates are integrated within the same device architecture. The gates share common structural elements and can be formed using the same polysilicon deposition and lithography processes, eliminating the need for additional separate lithography layers and reducing processing costs.
Solution Approach 2:
The patent designs the gate structure such that the first and second gates serve multiple functions: they independently control different regions of the device, work together to modulate current flow, and can be formed using the same manufacturing processes. This multi-functionality reduces the need for specialized additional processing steps.
3Ease of operation
If shallow trench-like gate is led out above wafer plane, then gate separation is achieved, but subsequent process implementation becomes difficult
Solution Approach 1:
The patent positions the second gate specifically within the drift region rather than leading it out above the wafer plane. This local placement allows the gate to perform its control function in the appropriate region while maintaining a flat surface profile that is compatible with subsequent photolithography and etching processes. The gate structure is optimized for its specific location rather than being uniformly elevated.
Data Source
Figure 1
Figure 2A
Figure 2B~2C
AI summary
A VDMOS device and a manufacturing method therefor. The manufacturing method comprises: forming a groove in a semiconductor substrate, the groove comprising a first groove area, a second groove area, a third groove area, a fourth groove area and a fifth groove area; successively forming a first insulation layer, a first polycrystalline silicon layer and a second insulation layer on the semiconductor substrate; removing some of the second insulation layer until the first polycrystalline silicon layer is exposed; removing some of the first polycrystalline silicon layer, the remaining first polycrystalline silicon layer forming a first electrode; forming a third insulation layer on the semiconductor substrate, removing some of the third insulation layer, the second insulation layer and the first insulation layer, so that the top of the first polycrystalline silicon layer is higher than the top of the first insulation layer and the second insulation layer; and successively forming a gate oxide layer and a second polycrystalline silicon layer on the semiconductor substrate, and removing some of the second polycrystalline silicon layer, exposing the gate oxide layer located on the surface of the semiconductor substrate and the top of the second insulation layer, the remaining second polycrystalline silicon layer forming a second electrode.