Trench Gate VDMOSFET with Flush Gate Electrode
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Solution Overview
Problem
Conventional semiconductor devices with trench gate VDMOSFETs face a trade-off between reducing on-resistance and gate capacitance, where decreasing one parameter often increases the other, making it difficult to achieve low-voltage, high-speed switching operations without risking dielectric breakdown.
Innovation Solution
The semiconductor device design features a gate electrode with its bottom surface flush with the upper surface of the conductivity type layer, reducing parasitic capacitance by opposing the gate electrode to the conductivity type layer only through the gate insulating film on the bottom surface of the gate trench, while maintaining the on-resistance unchanged.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the gate insulating film thickness is reduced to decrease on-resistance, then the on-resistance decreases, but the dielectric breakdown risk increases
Solution Approach 1:
The gate electrode bottom surface is positioned flush with the upper surface of the first conductivity type layer, changing the spatial relationship from the conventional configuration where the gate electrode extends below. This dimensional adjustment reduces the overlapping area between the gate electrode and the first conductivity type layer, thereby reducing parasitic capacitance without requiring further reduction of gate insulating film thickness, thus maintaining dielectric reliability while improving electrical performance.
2Speed
If the gate capacitance is reduced to improve switching speed, then the gate charge quantity decreases, but the on-resistance increases
Solution Approach 1:
By positioning the gate electrode bottom surface flush with the upper surface of the first conductivity type layer, the invention reduces the vertical overlapping dimension between the gate electrode and the conductivity type layer. This reduces the parasitic capacitance component without affecting the horizontal channel formation, thereby reducing gate charge quantity and improving switching speed while maintaining on-resistance through proper channel design.
3Manufacturing precision
If the gate electrode is positioned deeper in the gate trench to increase channel control, then the channel control improves, but the parasitic capacitance increases
Solution Approach 1:
The invention optimizes the vertical position of the gate electrode by positioning its bottom surface flush with the upper surface of the first conductivity type layer. This dimensional optimization reduces the overlapping area between the gate electrode and the conductivity type layer, thereby reducing parasitic capacitance while maintaining effective channel control through the gate insulating film interface.
Data Source
AI summary
A semiconductor device includes a first conductivity type layer of a first conductivity type, a body layer of a second conductivity type formed on the first conductivity type layer, a gate trench passing through the body layer so that the deepest portion thereof reaches the first conductivity type layer, a source region of the first conductivity type formed around the gate trench on the surface layer portion of the body layer, a gate insulating film formed on the bottom surface and the side surface of the gate trench, and a gate electrode embedded in the gate trench through the gate insulating film, and the bottom surface of the gate electrode and the upper surface of the first conductivity type layer are flush with each other.