Self-Aligned VDMOSFET Source-Body Layout for Shorter Channels
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Solution Overview
Problem
Existing Vertical Double Diffused Metal Oxide Semiconductor Field Effect Transistors (VDMOSFETs) face challenges in achieving self-alignment of the source and body regions, leading to current asymmetry, increased channel resistance, and on-resistance, which hinders device miniaturization and reliability.
Innovation Solution
A novel process technology that involves a simple thermal oxidation process and etching to achieve self-alignment of the source and body regions in VDMOSFETs, allowing for reduced channel length and improved process flexibility without increasing the channel length or cell pitch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high annealing temperature (1600°C) is used to reduce defects and activate impurities in SiC VDMOSFET, then reliability is improved, but source and body regions become misaligned causing current asymmetry
Solution Approach 1:
The patent performs source and body ion implantations before the high-temperature annealing process. By completing the alignment-critical implantation steps prior to thermal processing, the method ensures that subsequent annealing does not cause diffusion-induced misalignment, thus maintaining manufacturing precision while achieving the reliability benefits of high-temperature defect reduction and impurity activation.
2Length of moving object
If source and body regions are made self-aligned, then channel length can be reduced improving device miniaturization, but conventional methods require longer channel length to avoid misalignment
Solution Approach 1:
The patent implements source and body ion implantations before high-temperature annealing, establishing precise self-alignment early in the process. This preliminary alignment enables significant channel length reduction (to less than 0.5 μm) while maintaining current symmetry, as the subsequent annealing step does not disrupt the already-established alignment.
3Reliability
If longer channel length is used to avoid misalignment, then reliability is maintained, but channel resistance and on-resistance increase
Solution Approach 1:
By performing source and body implantations before high-temperature annealing, the patent achieves precise self-alignment that enables short channel length operation. This eliminates the need for longer channels as a compensatory measure, thereby reducing channel resistance and on-resistance while maintaining current symmetry and device reliability.
4Reliability
If conventional ion implantation process is used, then defects are reduced and impurities activated, but source and body regions cannot be self-aligned
Solution Approach 1:
The patent resequences the process steps by completing source and body ion implantations before the high-temperature annealing treatment. This preliminary action allows the implantation masks to define precise self-alignment boundaries that are not disrupted by subsequent thermal diffusion, thereby achieving both defect reduction/impurity activation and accurate source-body alignment simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed process effectively achieves self-alignment of the source and body regions, reducing channel length to less than 0.5 μm, minimizing surface damage, improving channel current, and reducing on-resistance, thereby enhancing device reliability and miniaturization.
Implementation Method 1
performing a thermal oxidation process so that the unoxidized material layer is oxidized to form a first insulation layer and a second insulation layer
Data Source
AI summary
A source-body self-aligned method of a VDMOSFET is provided. A pad layer and an unoxidized material layer are sequentially formed on an epitaxial layer on a semiconductor substrate. A lithography process is then carried out for patterning. Later, a thermal oxidation process is employed such that the unoxidized material layer is oxidized to form oxidation layers. Then, a source ion implantation process is performed, and a wet etching is used to remove the oxidation layers before successively employing a body ion implantation process. By using the process method disclosed in the present invention, it achieves to form the source region and the body region which are self-aligned. Meanwhile, since process complexity of the invention is relatively low, process uniformity and process cost can be optimally controlled. In addition, the invention achieves to reduce channel length and on-resistance, thereby enhancing the reliability effectively.