Vector Accelerator Debugging With Packet-Limit Breakpoints
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Solution Overview
Problem
Existing machine learning systems or models, such as ANNs, rely heavily on CPUs for operations, leading to significant bandwidth consumption and increased power usage, necessitating a more efficient solution for mathematical operations.
Innovation Solution
An accelerator circuit, including an instruction memory, program counter control circuit, data memory, and vector circuit, uses a packet limit breakpoint to manage instruction execution, allowing for efficient debugging and resource optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If CPU is used to execute machine learning operations, then ease of operation is improved, but power consumption increases
Solution Approach 1:
The patent segments machine learning operations into distinct functional units including vector circuits for parallel data processing, scalar circuits for control operations, and dedicated memory structures. This segmentation allows the accelerator circuit to handle computationally intensive tasks independently from the CPU, reducing overall power consumption while maintaining ease of operation through specialized hardware for each function.
Solution Approach 2:
The patent introduces an accelerator circuit as an intermediary between the CPU and memory systems. This intermediary handles specific machine learning workloads, allowing the CPU to focus on higher-level control tasks while the accelerator manages data-intensive operations, thereby reducing CPU power consumption without sacrificing operational ease.
2Productivity
If CPU bandwidth is used for machine learning operations, then productivity is improved, but bandwidth consumption increases
Solution Approach 1:
The patent transitions from sequential CPU-based processing to parallel vector circuit processing, effectively adding a dimensional aspect to computation. Multiple data elements are processed simultaneously through vector operations, dramatically improving productivity while reducing the bandwidth burden on the CPU by handling data locally within the accelerator circuit's dedicated memory structures.
Solution Approach 2:
The patent merges storage and processing functions within the accelerator circuit by integrating vector and scalar circuits with dedicated memory structures. This merging eliminates the need for constant data transfer between separate CPU and memory components, reducing bandwidth consumption while maintaining high productivity through combined compute-storage architecture.
3Reliability
If breakpoint debugging is implemented in accelerator circuit, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent implements self-service debugging capabilities within the accelerator circuit through automated breakpoint detection and state capture mechanisms. The program counter control circuit automatically triggers breakpoints and captures circuit states without requiring external debugging equipment, improving reliability while minimizing the addition of complex external debugging infrastructure.
Data Source
AI summary
Embodiments of the present disclosure relate to debugging of an accelerator circuit using a packet limit breakpoint. A vector circuit reads a subset of instruction packets from an instruction memory and receives a portion of input data from a data memory corresponding to the subset of instruction packets. The vector circuit executes a set of vector operations in accordance with multiple instruction packets from the subset using data from the received portion of input data identified in the multiple instruction packets to generate output data. A program counter control circuit coupled to the instruction memory triggers a breakpoint in a program stored in the instruction memory causing the accelerator circuit to stop executing remaining instruction packets in the program following the multiple instruction packets responsive to a number of instruction packets executed in the program from a time instant of an event reaching a predetermined number.