Vector Accumulator Instructions for Large Integer Addition

The patent divides large number integers into multiple blocks and uses vector registers to store multiple blocks simultaneously. Each vector register contains multiple lanes, where each lane stores a block of the large number integer. This segmentation allows parallel processing of multiple blocks within a single instruction, resolving the contradiction between sequential processing accuracy and processing efficiency.

The patent transitions from scalar arithmetic (one block at a time) to vector arithmetic (multiple blocks simultaneously) by introducing a new dimension of parallelism. Vector registers provide multiple lanes that can process different blocks concurrently, effectively moving from one-dimensional sequential processing to multi-dimensional parallel processing, thereby improving processing efficiency while maintaining computation accuracy.

The patent merges the carry bit tracking functionality into the vector accumulation instructions themselves. The accumulate instructions (ACCT and ACCB) inherently handle carry propagation across block boundaries by designing the vector register architecture to support continuous carry chains through all lanes. This merging eliminates the need for separate carry tracking instructions, reducing instruction complexity while maintaining parallel processing capability.

The vector accumulate instructions serve multiple functions simultaneously: they perform arithmetic operations on multiple blocks in parallel, track carry bits across block boundaries, and produce final results all within a single instruction type. This multi-functionality reduces the total number of instructions needed compared to traditional vector arithmetic approaches that require separate instructions for each function.

The patent implements continuous carry propagation across all blocks within a single instruction execution. The vector register architecture is designed so that carry bits flow continuously from one lane to the next without interruption, allowing the computation to complete in one continuous action rather than requiring multiple discrete instructions. This continuity maintains computation completeness while minimizing processing time.

The patent prepares the vector registers in advance with all blocks of the large number integers loaded into appropriate lanes before the accumulate instruction is executed. The carry chain is pre-configured across all lanes, so when the instruction executes, all arithmetic operations and carry propagations occur simultaneously in a single clock cycle, eliminating the need for multiple sequential instructions and reducing processing time while ensuring complete computation.