Vector Address Generation Using Bit-Interleaved Memory Bank Segmentation
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Solution Overview
Problem
Existing methods for accessing binary data vectors in memory units with multiple banks face inefficiencies due to the need for overlapping addresses and complex address mapping, especially when dealing with power-of-2 strides, leading to increased operating cycles and reduced performance.
Innovation Solution
A method that uses bit-level XOR functions to determine offsets for each memory bank, allowing for parallel access to binary data vectors by shifting mapping table results and controlling multiplexer stages to shuffle data elements, enabling efficient access and storage across multiple memory banks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data vectors are accessed using power-of-2 strides in memory banks, then data access patterns match common workload requirements, but overlapping addresses occur causing access conflicts and reduced performance
Solution Approach 1:
The memory address space is segmented into multiple banks, and the patent applies bit-interleaved segmentation where specific bits of the address are used to select different banks. This segmentation strategy distributes data elements across banks to eliminate overlaps while maintaining power-of-2 stride access patterns.
Solution Approach 2:
The patent introduces a new dimension for address mapping by using bit-interleaved bank selection instead of traditional sequential or modulo-based approaches. This dimensional change in address interpretation allows simultaneous access to multiple banks without conflicts.
2Speed
If complex address mapping is used to handle power-of-2 strides, then data can be accessed in parallel across memory banks, but the address mapping complexity increases leading to more operating cycles
Solution Approach 1:
The patent replaces complex mechanical address mapping logic with a simpler bit-interleaved selection mechanism. Instead of using complex comparators and control logic, the system directly uses specific bits of the address to select banks, significantly reducing hardware complexity while maintaining parallel access capability.
Solution Approach 2:
The patent changes the address mapping parameters by reinterpreting which bits of the address correspond to bank selection versus offset within bank. This parameter reassignment simplifies the mapping function and reduces the number of operating cycles required.
3Adaptability or versatility
If multiple different power-of-2 strides are used to compose data vectors, then flexibility in data structure access is improved, but ensuring elements are stored in distinct banks becomes much more difficult
Solution Approach 1:
The patent creates a universal bit-interleaved addressing scheme that works for all power-of-2 strides. The same bank selection logic based on address bits handles different strides uniformly, providing multi-functionality without requiring separate management mechanisms for each stride type.
Solution Approach 2:
The address itself contains the bank selection information through its bit structure. The system uses the address bits directly to select banks, making the address self-sufficient for bank distribution without requiring additional control signals or management overhead.
Data Source
AI summary
A method for accessing a binary data vector in a memory unit comprising a plurality of memory banks in which the binary data vector is stored in portions includes receiving a start address of the binary data vector and a power-of-2-stride elements of the data vector and determining offsets, wherein the offsets are determined by applying a plurality of bit-level XOR functions to the start address resulting in a Z vector, using the Z vector for accessing a mapping table, and shifting mapping table access results according to a power-of-2-stride of the binary data vector. Additionally, the method includes determining a sequence of portions of the binary data vector in the n memory banks depending on a binary equivalent value of the Z vector, and accessing the binary data vector in the n memory banks of the memory unit in parallel.