Vector Arithmetic Processing Unit for Digital Pre-Distortion
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Solution Overview
Problem
Current systems for wireless base stations face inefficiencies in vector operation control and memory access, particularly in handling large vectors and matrices, which affects system performance and response time due to complex nonlinearities and memory effects in power amplifiers.
Innovation Solution
An integrated circuit with a DPD circuit that includes a vector arithmetic processing unit (APU) capable of performing complex domain vector arithmetic, utilizing a conjugate gradient method to solve for coefficients in pre-distortion models, and optimizing memory configuration for efficient parallelization of matrix operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If complex nonlinearities and memory effects in power amplifiers are handled using traditional vector operation control, then system coverage and functionality are maintained, but system performance and response time deteriorate due to inefficiencies in vector operation control and memory access
Solution Approach 1:
The system is segmented into distinct functional units: a vector arithmetic processing unit (APU) dedicated to vector operations, separate memory structures (instruction memory and data memory) for storing vectors and instructions, and a control unit. This segmentation allows each component to be optimized independently, with the APU handling complex vector arithmetic efficiently while memory structures are optimized for fast access patterns required by vector operations.
Solution Approach 2:
An intermediary instruction memory structure is introduced between the control logic and the vector data in memory. This instruction memory stores pre-computed vector operation instructions that guide the APU through complex nonlinearities and memory effects processing, enabling efficient execution without requiring complex real-time control logic.
2Speed
If large vectors and matrices are processed using conventional memory access methods, then data storage capacity is sufficient, but system response time deteriorates due to inefficient memory access patterns
Solution Approach 1:
The patent introduces a new dimension to memory organization by implementing specialized memory structures that align with vector operation requirements. Instead of conventional two-dimensional memory addressing, the system uses memory layouts optimized for sequential vector access patterns, enabling faster retrieval of large vector and matrix data without compromising storage capacity.
3Productivity
If traditional control methods are used for vector operations on large vectors, then implementation simplicity is maintained, but efficiency of vector operation control and memory access deteriorates
Solution Approach 1:
The patent replaces conventional software-based vector operation control with a dedicated hardware vector arithmetic processing unit (APU). This substitution of mechanical/control systems with specialized hardware architecture enables efficient execution of vector operations on large vectors while maintaining ease of operation through standardized instruction interfaces.
Data Source
AI summary
In described examples, an integrated circuit includes an output terminal coupled to an input of a power amplifier, a feedback terminal coupled to an output of the power amplifier, a data terminal that receives a data stream, and a digital pre-distortion (DPD) circuit. The DPD circuit includes a capture circuit, a DPD estimator responsive to the data stream and the feedback terminal, and a DPD corrector responsive to the DPD estimator. The DPD estimator includes an instruction memory configured to store instructions and a vector arithmetic processing unit (APU) coupled to the instruction memory. The vector APU includes vector memories, vector arithmetic blocks, and an instruction decode block. The vector arithmetic blocks include vector addition blocks and vector multiplication blocks. The instruction decode block is configured to cause the vector APU to perform complex domain vector arithmetic on vectors stored in the vector memories in response to the instructions.