Vector Array Access for 2D Data Processing Throughput
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Solution Overview
Problem
Existing data processing systems struggle to efficiently process two-dimensional arrays of data items, particularly in vector processing operations, where a single instruction is applied to multiple data items simultaneously, leading to inefficiencies compared to scalar processing.
Innovation Solution
A data processing apparatus and method that allows for accessing and processing two-dimensional storage arrays as vectors, utilizing vector processing circuitry to apply instructions to storage arrays of n x n locations, with optional predicate control and indexed access techniques, enabling efficient parallel processing of data items.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If vector processing operations are applied to two-dimensional arrays, then processing throughput is improved, but access complexity to storage locations increases
Solution Approach 1:
The patent transforms two-dimensional array access into one-dimensional linear array access by mapping 2D coordinates (row, column) to 1D linear indices. This dimensionality reduction allows vector processing units to access multiple elements simultaneously using linear addressing, thereby maintaining high throughput while simplifying the access mechanism.
Solution Approach 2:
The patent introduces an address generation unit (AGU) as an intermediary that automatically computes linear addresses from 2D array coordinates and vector indices. This mediator handles the complexity of address calculation, allowing the vector processing units to focus on data manipulation without directly managing complex 2D address computation.
2Ease of operation
If scalar processing is used for data items, then access simplicity is maintained, but processing efficiency deteriorates
Solution Approach 1:
The patent merges scalar processing simplicity with vector processing efficiency by allowing scalar instructions to operate on linearized 2D array data. The unified linear addressing scheme enables both scalar and vector operations to use the same simple addressing mechanism, while vector operations can still process multiple elements in parallel when needed.
3Productivity
If linear array access is used instead of two-dimensional array access, then vector processing efficiency is improved, but data organization flexibility is reduced
Solution Approach 1:
The patent implements dynamic data layout support by allowing the same linear addressing framework to accommodate different data organization schemes. The address generation unit can adapt to different stride patterns, block sizes, and data layouts, enabling efficient vector processing while maintaining flexibility in how data is organized in memory.
Data Source
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AI summary
Data processing apparatus comprises vector processing circuitry to access an array register having at least n x n storage locations, where n is an integer greater than one, the vector processing circuitry comprising: instruction decoder circuitry to decode program instructions; and instruction processing circuitry to execute instructions decoded by the instruction decoder circuitry. The instruction decoder circuitry is responsive to an array access instruction, to control the instruction processing circuitry to access, for a vector of n vector elements, a set of n storage locations each having a respective array location in the array register. The array location accessed for a given vector element of the vector is defined by one or more coordinates associated with the given vector element by one or more parameters of the array access instruction.