Vector Add-Compare-Select Instruction for Faster Viterbi Decoding
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Solution Overview
Problem
Existing Viterbi decoding processes in wireless telephones require multiple instructions to determine a preceding state, increasing processing time due to the need for separate add, compare, and select operations.
Innovation Solution
A single instruction, such as the 'vacsh' instruction, performs vector addition, subtraction, and comparison operations to determine a preceding state, allowing these operations to be executed in the same cycle and taking advantage of instruction-level parallelism in VLIW architectures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple separate instructions are used to perform add, compare, and select operations in Viterbi decoding, then each operation can be performed with dedicated logic, but the processing time increases and decoding speed decreases
Solution Approach 1:
The patent combines add, compare, and select operations into a single unified instruction (ASC instruction) that performs all three operations in one execution cycle. This merging eliminates the need for multiple separate instructions and reduces the total number of execution cycles required for Viterbi decoding, directly addressing the time loss problem while maintaining decoding accuracy through the integrated operation sequence.
Solution Approach 2:
The ASC instruction is designed as a multi-functional instruction that can perform addition, comparison, and selection operations within a single instruction cycle. This universal instruction replaces multiple specialized instructions, reducing instruction fetch overhead and improving decoding speed without sacrificing the precision of individual operations.
2Reliability
If multiple instructions are used to determine preceding state, then each operation can be optimized independently, but the code size increases and instruction fetch overhead increases
Solution Approach 1:
The patent merges multiple instructions into a single ASC instruction that encapsulates add, compare, and select operations. This reduces the total instruction count and code size while maintaining decoding reliability through the integrated operation sequence that preserves the logical dependencies between operations.
Solution Approach 2:
The unified ASC instruction serves multiple functions (addition, comparison, selection) that previously required separate instructions. This reduces instruction fetch overhead and simplifies the instruction stream while maintaining the reliability of each individual operation through proper internal sequencing.
3Productivity
If separate add, compare, and select instructions are used, then each operation can be pipeline-optimized, but the total execution cycles increase
Solution Approach 1:
The patent combines add, compare, and select operations into a single ASC instruction that executes in one cycle, eliminating the sequential execution of multiple instructions. This merging directly reduces the total execution duration and increases decoding throughput by reducing instruction fetch and decode overhead.
Solution Approach 2:
The unified ASC instruction enables continuous execution of decoding operations without the interruptions caused by multiple instruction boundaries. The integrated operation sequence maintains continuous data flow and eliminates idle cycles between operations, improving overall productivity.
Data Source
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AI summary
An apparatus includes memory storing an instruction that identifies a first register, a second register, and a third register. Upon execution of the instruction by a processor, a vector addition operation is performed by the processor to add first values from the first register to second values from the second register. A vector subtraction operation is also performed upon execution of the instruction to subtract the second value from third values from the third register. A vector compare operation is also performed upon execution of the instruction to compare results of the vector addition operation to results of the vector subtraction operation.