Vector Evaluation of Assertions for Parallel Circuit Verification
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Solution Overview
Problem
Assertion evaluation during design verification is inefficient, as existing methods do not effectively utilize parallel processing to evaluate semantically equivalent assertions, leading to prolonged verification times.
Innovation Solution
Identify semantically equivalent assertions and determine a set of vectors based on these assertions, allowing for parallel evaluation through vector operations, which can include bitwise logical operations supported by general-purpose processors or specialized vector processors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If traditional sequential assertion evaluation methods are used, then verification correctness is maintained, but verification time becomes excessively long
Solution Approach 1:
The patent segments the assertion evaluation process by identifying semantically equivalent assertions that can be grouped together. These grouped assertions are then evaluated simultaneously using vector operations, dividing the sequential evaluation task into parallel executable units that reduce overall verification time while maintaining correctness.
Solution Approach 2:
The patent merges semantically equivalent assertions into unified evaluation units. By combining multiple equivalent assertions into a single vector operation, the system evaluates them simultaneously rather than sequentially, directly addressing the time efficiency problem while preserving the semantic meaning and verification accuracy of each individual assertion.
2Productivity
If parallel evaluation of semantically equivalent assertions is implemented, then verification efficiency improves, but system complexity increases
Solution Approach 1:
The patent uses copying by creating vector representations of semantically equivalent assertions. Instead of implementing complex parallel processing logic for each assertion, the system copies assertions into a standardized vector format that can be processed in parallel using simple, uniform operations, thereby reducing system complexity while maintaining parallel evaluation capabilities.
Solution Approach 2:
The patent changes the parameter representation of assertions from individual logical expressions to vector formats. This parameter transformation enables parallel processing by representing multiple semantically equivalent assertions in a unified mathematical structure that can be manipulated simultaneously through vector operations, simplifying the overall system architecture.
Data Source
AI summary
Systems and techniques for evaluating assertions during circuit verification are described. During operation, m semantically equivalent assertions can be identified, wherein each of the m semantically equivalent assertions is evaluated using n logical expressions. Next, a set of vectors based on the m semantically equivalent assertions can be determined, wherein each vector element corresponds to a logical expression that is used for evaluating one of the m semantically equivalent assertions. The m semantically equivalent assertions can then be evaluated, in parallel, using the set of vectors.