Vector Atomic Memory Operations for Unsupported Data Lengths
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Solution Overview
Problem
Current vector computers are limited in handling data lengths other than 32 and 64 bits, requiring scalar mode for operations on 8 or 16 bit data, which restricts the efficiency of vector processing due to issues like false conflicts when smaller data words are packed into larger vector hardware supported data words.
Innovation Solution
The introduction of vector atomic memory operations (VAMO) instructions that allow for atomic operations on multiple memory locations simultaneously, enabling vectorization of scalar loops and handling of unsupported data lengths by using strided and indexed vectors, and additional decode logic to manage these operations efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If scalar mode is used for operations on 8 or 16 bit data, then data length compatibility is achieved, but processing efficiency deteriorates
Solution Approach 1:
The patent segments a 64-bit vector register into multiple smaller data elements (e.g., eight 8-bit elements or four 16-bit elements). This allows the vector hardware to process multiple small data elements simultaneously in parallel, achieving both data length compatibility and high processing efficiency that would otherwise require scalar mode
Solution Approach 2:
The patent introduces a new dimension of data organization by packing multiple small data elements into a single vector register element and using bitwise operations to manipulate individual elements within the packed structure. This dimensional transformation enables small data element processing through vector hardware without requiring scalar mode
2Productivity
If smaller data words are packed into larger vector hardware supported data words, then vector processing capability is utilized, but false conflicts occur
Solution Approach 1:
The patent applies local quality by using separate mask registers for different data elements within the same vector register. Each mask register controls access to specific elements independently, allowing precise control over which packed elements are read or written, thereby preventing false conflicts between simultaneous operations on different elements
Solution Approach 2:
The patent introduces mask registers as intermediary control structures between the vector operations and the packed data elements. These masks act as mediators that selectively enable or disable access to specific elements, preventing false conflicts by ensuring that only authorized elements are accessed during simultaneous operations
3Device complexity
If vector hardware supports only 32 and 64 bit data, then hardware complexity is reduced, but adaptability to different data lengths deteriorates
Solution Approach 1:
The patent makes the existing 32/64-bit vector hardware universal by implementing software-based packing and unpacking mechanisms that allow the same hardware to process multiple data lengths (8-bit, 16-bit, 32-bit, 64-bit). The vector register can universally hold any data type by appropriate packing, eliminating the need for separate hardware paths for each data length
Data Source
AI summary
A system and method of compiling program code, wherein the program code includes an operation on an array of data elements stored in memory of a computer system. The program code is scanned for an equation which operates on data of lengths other than the limited number of vector supported data lengths. The equation is then replaced with vectorized machine executable code, wherein the machine executable code comprises a nested loop and wherein the nested loop comprises an exterior loop and a virtual interior loop. The exterior loop decomposes the equation into a plurality of loops of length N, wherein N is an integer greater than one. The virtual interior loop executes vector operations corresponding to the N length loop to form a result vector of length N, wherein the virtual interior loop includes one or more vector atomic memory operation (AMO) instructions, used to resolve false conflicts.