Vector FP32-to-BF16 Conversion Instructions for Memory-Efficient Compute
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Solution Overview
Problem
Existing processor architectures face inefficiencies in converting single-precision floating-point data to 16-bit floating-point format, particularly in applications requiring data parallelism, leading to suboptimal memory utilization and performance in tasks like machine learning.
Innovation Solution
Implementing a vector packed data format-convert instruction (VCVTNEPS2BF16 and VCVTNE2PS2BF16) that facilitates the conversion of single-precision elements to 16-bit floating-point format, allowing balanced storage in vector registers and reducing memory requirements through truncation and rounding, while maintaining computational accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If single-precision floating-point data is used for computations, then computational accuracy is maintained, but memory utilization is inefficient and power consumption increases
Solution Approach 1:
The patent changes the data precision parameter from single-precision (32-bit) to 16-bit floating-point format for storage and processing. This parameter change enables reduced memory utilization while maintaining acceptable computational accuracy for many machine learning applications, directly resolving the contradiction between precision and memory efficiency.
Solution Approach 2:
The patent applies partial precision (16-bit instead of full 32-bit) when memory resources are constrained. This partial action approach uses sufficient precision for the application domain while reducing overall memory requirements, achieving a balance between accuracy and memory utilization.
2Measurement precision
If single-precision floating-point data is used for computations, then computational accuracy is maintained, but power efficiency deteriorates
Solution Approach 1:
The patent changes the data precision parameter from single-precision (32-bit) to 16-bit floating-point format. This parameter change reduces the amount of data that needs to be processed, transferred, and stored, thereby reducing power consumption while maintaining acceptable computational accuracy for machine learning workloads.
Solution Approach 2:
The patent uses partial precision (16-bit) instead of full precision (32-bit) to reduce computational workload and energy consumption. This approach provides sufficient accuracy for the application while significantly improving power efficiency.
3Productivity
If data parallelism is implemented with standard floating-point formats, then computational performance is achieved, but memory requirements increase
Solution Approach 1:
The patent changes the data format parameter to 16-bit floating-point, which reduces the memory footprint by half compared to 32-bit formats. This enables larger datasets and more extensive data parallelism operations to fit in available memory, thereby maintaining computational performance while reducing memory requirements.
Solution Approach 2:
The patent applies partial precision (16-bit) to reduce memory requirements for data parallelism operations. This partial action enables more data to be processed simultaneously within memory constraints, improving productivity without requiring proportional increases in memory resources.
Data Source
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AI summary
Disclosed embodiments relate to a processor, a system on a chip and a system for executing a format conversion instruction. In one example, a processor comprises: a control register to specify a rounding mode; fetch circuitry to fetch a format conversion instruction; a decode unit to decode the format conversion instruction, the format conversion instruction having an opcode, a first field to specify a source vector register, a second field to specify a destination vector register, the source vector register to store a source vector having a plurality of 32-bit single-precision floating point data elements; and execution circuitry coupled with the decode unit. The execution circuitry to execute the decoded format conversion instruction to: convert the 32-bit single-precision floating point data elements of the source vector to corresponding 16-bit floating point data elements, according to the rounding mode specified by the control register, the 16-bit floating point data elements having a format, the format including a sign bit, an 8-bit exponent, seven explicit mantissa bits, and one implicit mantissa bit; and store the 16-bit floating point data elements in a first half of a result in the destination vector register.