Vector Buffer Architecture for Memory-Indexed Sequence Analysis
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Solution Overview
Problem
Existing sequence analysis accelerators are limited by their inability to efficiently handle memory-indexed instructions, lack versatility in accommodating multiple algorithms, and are constrained to processing short sequences or specific data types, failing to adapt to emerging sequencing technologies and algorithms like WFA and BiWFA.
Innovation Solution
A system combining a vector accelerator architecture with a general-purpose CPU's pipeline, incorporating improved vector instructions and hardware buffers to optimize memory access operations, supporting both short and long sequence analyses, and enabling flexible integration of new algorithms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If hardware architecture is tailored to a singular sequencing algorithm, then execution efficiency for that algorithm is improved, but versatility to accommodate multiple algorithms deteriorates
Solution Approach 1:
The hardware architecture implements a universal buffer system that can serve multiple sequencing algorithms (WFA, BiWFA, Smith-Waterman, etc.) through a unified interface. The buffer is designed with configurable parameters including number of buffers, buffer size, and number of read ports, allowing it to adapt to different algorithm requirements while maintaining a single hardware structure. This enables one hardware design to efficiently support multiple algorithms without requiring algorithm-specific hardware modifications.
2Productivity
If hardware is optimized for short input sequences, then processing speed for short sequences is improved, but capability to handle long sequences deteriorates
Solution Approach 1:
The buffer architecture employs dynamic configuration parameters that can be adjusted based on sequence length requirements. The number of buffers, buffer size, and number of read ports are configurable to match the specific needs of short or long sequence processing. This dynamic adaptability allows the same hardware to optimize performance for both short Illumina reads and long PacBio HiFi or Oxford Nanopore Duplex sequences without requiring separate hardware designs.
3Adaptability or versatility
If scatter-gather memory instructions are used for memory access, then flexibility in data retrieval is improved, but latency and overhead increase
Solution Approach 1:
The system pre-loads sequence data into the universal buffer before the main algorithm execution begins. This preliminary action ensures that data is readily available in high-speed buffer memory during algorithm processing, eliminating the need for frequent scatter-gather memory operations during execution. The buffer is configured to hold the working set of data needed for the algorithm, reducing memory access latency while maintaining the flexibility to access any position in the sequence through the buffer's random access capability.
Data Source
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AI summary
The present invention relates to a system (1) for accelerating the execution of an algorithm, adapted to connect to the vector datapath of a Vector Processing Unit (VPU) (2) comprising a Vector Register File (VRF) (3) and an arithmetic logic unit (ALU) (4). The system (1) comprises a data encoder (6) connected to the VRF (3), one or more direct-mapped buffers (5) connected to the VRF (3) and to the data encoder (6). The data encoder (6) receives data from the VRF (3), applies a static-bit encoding and sends the encoded data to the one or more buffers (5); the access control module (7) transfers data from the VRF (3) to the one or more buffers (5) and/or instructions from the buffers (5) to the ALU (4); and the one or more buffers (5) receive data from the VRF (3) and/or from the data encoder (6), store it in a position within the buffer (5) and deliver it to the access control module (7).