Vector Caching Unit for Neural Network Acceleration

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Solution Overview

Problem

Current methods for performing logical operations in multilayer neural networks, such as using general-purpose processors or GPUs, face performance bottlenecks due to low single-processor performance and limited on-chip caching, leading to inefficient power consumption and data transfer issues.

Innovation Solution

A neural network acceleration processor is designed with a vector caching unit and a computation module that includes comparers to perform vector operations efficiently, storing vectors on-chip and comparing elements to generate output results based on predetermined conditions, thereby optimizing vector operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a general-purpose processor is used to perform logical operations for vectors, then the system maintains versatility for various computations, but the processing performance is insufficient to meet requirements for vectors with large number of elements

Engineering Contradiction:
Improvecomputational versatilityVSAvoidvector processing performance
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The system is divided into a general-purpose processor for control and instruction management, and a dedicated vector processing unit with specialized hardware for actual vector operations. This segmentation allows the general-purpose processor to maintain versatility while the dedicated unit provides high-performance vector processing capability.

Inventive Principle:
Principle #1Segmentation

2Productivity

If a GPU with general-purpose register file and stream processing unit is used, then SIMD instructions can be executed to support MNN algorithms, but the limited on-chip caching causes repeated data movement from off-chip resulting in huge power consumption

Engineering Contradiction:
Improvealgorithm execution capabilityVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The vector caching unit pre-loads vector elements from off-chip memory into on-chip cache before processing operations. This preliminary action ensures that data is readily available during computation, eliminating repeated data movement and reducing power consumption while maintaining algorithm execution capability.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If a GPU with limited on-chip caching is used, then the system can execute SIMD instructions, but data must be repeatedly moved from off-chip making off-chip bandwidth the main performance bottleneck

Engineering Contradiction:
ImproveSIMD instruction executionVSAvoiddata transfer speed
Core Design Contradiction:
ProductivityVSSpeed

Solution Approach 1:

A dedicated vector caching unit acts as an intermediary between off-chip memory and the computation module. This intermediary component buffers vector data, allowing SIMD instructions to execute efficiently while minimizing repeated access to off-chip memory and reducing the impact of off-chip bandwidth limitations.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11409524B2Apparatus and methods for vector operations
Publication Date: 2022.08.09 CAMBRICON TECH CO LTD
  • US11409524B2 patent drawing
  • US11409524B2 patent drawing
  • US11409524B2 patent drawing

AI summary

Aspects for vector operations in neural network are described herein. The aspects may include a vector caching unit configured to store a vector, wherein the vector includes one or more elements. The aspects may further include a computation module that includes one or more comparers configured to compare the one or more elements to generate an output result that satisfies a predetermined condition included in an instruction.