Vector Signaling Code FEC with Incremental Syndrome Updates
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Solution Overview
Problem
High-speed chip-to-chip communication systems face challenges in minimizing communication errors due to high Bit Error Rates (BER) and latency associated with existing error correction methods, particularly in low BER environments where traditional Forward Error Correction (FEC) techniques introduce significant latency and computational power consumption.
Innovation Solution
The implementation of a vector signaling code system using a check matrix with elements from the Galois field GF(2^n) for error correction, which performs incremental updates of error correction syndrome values during transmission and reception, allowing for efficient error detection and correction with reduced latency by modifying data bits based on error correction syndrome values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional Forward Error Correction (FEC) techniques are used for error correction in high-speed chip-to-chip communication, then error correction capability is improved, but latency increases significantly
Solution Approach 1:
The patent segments the error correction process into incremental updates performed on individual codewords as they are received, rather than waiting for complete data blocks. This allows error correction to proceed in parallel with data reception, reducing overall latency while maintaining correction capability.
Solution Approach 2:
The patent performs preliminary error correction calculations during the reception and serialization process itself, computing syndrome values incrementally as data arrives. This preliminary action eliminates the need for separate post-reception error correction processing, thereby reducing latency.
2Reliability
If traditional Forward Error Correction (FEC) techniques are used for error correction, then error correction capability is improved, but computational power consumption increases
Solution Approach 1:
The patent divides the computational workload into smaller incremental updates processed on individual codewords rather than computing full syndrome values for entire data blocks. This segmentation reduces the peak computational power required at any given moment while maintaining overall error correction capability.
Solution Approach 2:
The patent maintains continuous error correction computation during data reception and transmission, utilizing the natural flow of data to perform calculations incrementally. This continuous processing avoids idle computational cycles and optimizes power efficiency by keeping the correction logic active only when data is being processed.
3Loss of time
If vector signaling code system with incremental FEC is used, then latency is reduced, but system complexity increases
Solution Approach 1:
The patent merges the error correction functionality with the existing vector signaling code transmission and reception processes. By integrating FEC calculations into the serialization and deserialization pipelines, the system achieves low-latency error correction without adding separate independent processing stages, thereby limiting complexity growth.
4Speed
If high-speed data transmission is implemented, then transmission speed is improved, but Bit Error Rate increases
Solution Approach 1:
The patent introduces syndrome values as intermediary computational structures that mediate between the high-speed data transmission and error detection/correction processes. These syndrome values provide a compact representation of error conditions, enabling efficient error handling that maintains reliability despite high transmission speeds.
Data Source
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AI summary
Decoding sequentially received vector signaling codewords to obtain sequential sets of data bits, wherein elements of each vector signaling codeword are received in parallel over a plurality of wires, generating an incremental update of a plurality of error correction syndrome values based on each sequential set of data bits according to a check matrix, and upon decoding of a final vector signaling codeword, performing a final incremental update of the plurality of error correction syndrome values and responsively modifying data bits within the sequential sets of data bits by selecting a set of data bits from the sequential sets of data bits according to a symbol position index determined from the plurality of error correction syndrome values, the selected set of data bits altered according to a bit error mask determined from a first error correction syndrome value of the plurality of error correction syndrome values.