Vector Compress2 Instructions for Dual Memory Store Overhead
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Solution Overview
Problem
Current vectorization of compress patterns using single compress operations is inefficient due to overhead from mask negation, popcnt, and LEA instructions, especially when dealing with multiple memory locations, which limits performance in applications like Molecular Dynamics codes and bin sorting algorithms.
Innovation Solution
The introduction of vector compress2 and expand2 instructions that allow contiguous stores to two different memory destinations using a single control mask and two input base pointers, eliminating the need for separate instructions to update pointers and negate masks, thereby performing auxiliary operations in a single pass through the source vector.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If single compress operation is used for vectorization, then code simplicity is maintained, but execution overhead increases due to separate pointer update and mask negation instructions
Solution Approach 1:
The patent combines multiple separate operations (compress, pointer increment, mask negation) into a single vector compress2 instruction that performs compression to two memory destinations simultaneously, eliminating the need for separate pointer update and mask negation instructions and reducing overall execution overhead
Solution Approach 2:
The vector compress2 instruction serves multiple functions in a single operation: it compresses source elements to two different memory destinations based on a control mask, updates both destination pointers, and manages mask states, making the instruction highly versatile for various compression patterns
2Reliability
If two separate compress operations are used for sorting into 2 bins, then correct bin sorting is achieved, but pointer update overhead doubles
Solution Approach 1:
The patent merges two separate compress operations into a single vector compress2 instruction that simultaneously sorts elements into two bins, with both destination pointers being updated in one operation rather than requiring separate update instructions for each compress operation
Solution Approach 2:
The instruction segments the compression destination into two separate memory locations (first and second destination operands), allowing elements to be routed to different bins based on the control mask while maintaining a unified instruction structure that handles both destinations efficiently
3Stability of the object's composition
If contiguous stores to two memory locations are performed using separate instructions, then memory organization is maintained, but instruction overhead increases
Solution Approach 1:
The vector compress2 instruction provides universal functionality for storing elements to either of two memory locations based on a control mask, maintaining organized memory structures while reducing the number of instructions needed compared to separate store operations
Data Source
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AI summary
Disclosed embodiments relate to vector compress2 and expand2 instructions with two memory locations. In one example, a system includes a memory and a processor that includes circuits to fetch, decode, and execute the instruction that includes an opcode, a first destination operand identifier, a second destination operand identifier, a source operand identifier, and a control mask, wherein, for each element of the source operand, the execution circuit is to generate a result by performing one of compression and expansion of the element; and, based on the value of a bit of the control mask corresponding to the element, store the result to a first location identified by the first destination operand identifier and increment the first destination operand identifier by a size of the result, and, otherwise, store the result to a second location identified by the second destination operand identifier and increment the second destination operand identifier by the size of the result.