Vector Packed Concatenate-Shift for Modular Multiplication
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Solution Overview
Problem
Current instruction set architectures lack support for dual-source concatenation and shift of specific bits less than the length of one data lane, leading to inefficiencies in element-wise modular multiplication, particularly in polynomial multiplication for fully homomorphic encryption applications.
Innovation Solution
Introduce a set of instructions for vector packed concatenate and shift operations that allow specific bits from two sources to be concatenated and shifted, optimizing modular multiplication by reducing storage needs and enabling efficient extraction of desired results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional instruction set architectures are used for element-wise modular multiplication, then operations can be performed, but the process requires multiple separate instructions and intermediate storage, reducing efficiency
Solution Approach 1:
The patent combines concatenation and shift operations into a single dual-source concatenate and shift instruction. This merging of previously separate operations (concatenation followed by shift) into one atomic instruction reduces the instruction sequence length and improves execution efficiency for element-wise modular multiplication operations
2Manufacturing precision
If dual-source concatenation with specific bit selection is implemented, then precise bit manipulation is achieved, but the instruction set complexity increases
Solution Approach 1:
The patent enables selective manipulation of specific bit portions (fields) within data elements by allowing different source operands to contribute different numbers of bits to the result. This local quality approach allows precise control over which bits are concatenated and shifted, optimizing operations like modular multiplication where only specific bit ranges are needed
3Reliability
If intermediate results are stored in full precision, then accuracy is maintained, but storage requirements increase
Solution Approach 1:
The patent extracts only the necessary number of bits from intermediate concatenation results based on the specific computational requirements. By allowing the destination operand to specify exactly how many bits are needed (rather than storing all bits from concatenation), the instruction reduces storage requirements while maintaining the precision needed for the specific application
Data Source
AI summary
Apparatus and method for performing vector packed concatenate and shift of portions of quadwords are described herein. An apparatus embodiment includes decoder circuitry to decode a first instruction and execution circuitry to execute the decoded instruction. The execute circuitry includes concatenation circuitry to concatenate a first field from each of a first plurality of data elements with a second field from a corresponding data element of the second plurality of data elements to generate a plurality of concatenated results, and shift circuitry to shift each of the plurality of concatenated results by a number of bit positions specified by a corresponding shift value to generate a plurality of shifted results, wherein a select plurality of bits from each of the plurality of shifted results is stored in a corresponding data element position of a destination register.