Vector Data Packing in Signal Processors
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Solution Overview
Problem
Signal processing applications face inefficiencies in memory usage due to mismatched word sizes between data elements and memory locations, leading to increased memory requirements and complex wiring needs in SIMD processors.
Innovation Solution
A method involving bit exchange and shuffling operations to rearrange data elements within vectors, allowing efficient storage and loading without requiring additional complex data lines, by transferring bits between subsequent register elements and merging them to match memory storage sizes, utilizing an exchange facility and shuffle unit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If data elements are mapped directly to memory locations with larger word sizes, then storage simplicity is improved, but memory requirements increase significantly
Solution Approach 1:
The invention segments the data elements into smaller units that can be efficiently packed into memory locations. Instead of mapping entire 16-bit data elements to 16-bit memory locations when smaller sizes (e.g., 10-bit) are sufficient, the data is divided and packed multiple smaller elements into each memory location, reducing overall memory requirements while maintaining data integrity.
Solution Approach 2:
The invention changes the parameter of data element size to match memory location size by implementing compression and packing mechanisms. Data elements are transformed from their original size to compressed representations that fit efficiently into memory locations, optimizing the match between data element size and memory location size.
2Quantity of substance
If compression is applied to match data element size with memory location size, then memory usage efficiency is improved, but device complexity increases due to required multiplexers and wiring
Solution Approach 1:
The invention implements a universal compression and packing mechanism that can handle multiple data element sizes (e.g., 8-bit, 10-bit, 12-bit) using the same hardware structure. The multiplexer and packing logic are designed to be size-agnostic, allowing the system to adapt to different data element sizes without requiring separate dedicated circuits for each size, thereby reducing overall device complexity.
Solution Approach 2:
The invention introduces dynamic control mechanisms where the compression and packing behavior adapts based on the actual data element size being processed. The system dynamically selects appropriate packing strategies and multiplexer configurations based on the data size, allowing flexible optimization without hardcoding separate paths for each possible data size.
3Adaptability or versatility
If multiple compression formats for different data element sizes are supported, then adaptability is improved, but the number of required multiplexers and data lines increases
Solution Approach 1:
The invention designs a universal compression and packing unit that can handle multiple data element sizes (8-bit, 10-bit, 12-bit, etc.) through a single hardware structure. The multiplexer is configured to dynamically select and apply the appropriate packing strategy based on the input data size, eliminating the need for separate dedicated compression circuits for each data size and reducing the total number of multiplexers required.
Data Source
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AI summary
A method for storing a vector of process data elements (Dl,..., D8) that have a size of n bits from a register file (RF) into a memory (M) is described. The memory is arranged for storage of a vector of storage data elements in locations (Ml,..., M5) having a size of m bits, wherein m>n. The method comprises the steps of: exchanging bits (S2) between process data elements in the vector stored in mutually subsequent register elements, the exchanging resulting in a vector of modified data elements (DmI,..., Dm8), shuffling (S3) groups of k subsequent bits in the resulting vector, - storing (S4) the resulting shuffled vector of modified data elements as a vector of storage data elements in the memory (M).