Vector Data Splicing Instructions for SIMD Alignment

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Solution Overview

Problem

Existing SIMD instructions face inefficiencies due to misaligned vector data, leading to incomplete utilization of vector registers and potential misuse of invalid information, which hinders effective digital signal processing.

Innovation Solution

A data splicing instruction apparatus and method that allows for flexible splicing of vector data by specifying positions and lengths of parts to be acquired from source vectors, using a splicing indicator, enabling efficient alignment and utilization of vector registers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If vector data is arranged closely at addresses with no space left to maximize address space utilization, then memory space efficiency is improved, but vector data alignment is lost causing elements to be misaligned when loaded into vector registers

Engineering Contradiction:
Improveaddress space utilizationVSAvoiddata alignment
Core Design Contradiction:
Quantity of substanceVSManufacturing precision

Solution Approach 1:

The patent segments the vector data loading process into multiple steps: first loading data into a temporary register, then using a splicing instruction to extract properly aligned elements and transfer them to the target vector register. This segmentation allows the system to maintain close address spacing while still achieving proper alignment through the intermediate extraction step.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a temporary register as an intermediary between memory and the target vector register. Data is first loaded into this intermediate register, then the splicing instruction uses control data to extract specific aligned elements and transfer them to the final destination, thereby resolving the alignment issue without changing the memory layout.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If vector data is loaded into vector register to perform processing, then data processing capability is improved, but invalid information remains in the register when total data size is not a multiple of register bit width

Engineering Contradiction:
Improvedata processing capabilityVSAvoiddata validity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The splicing instruction extracts only the valid data elements from the loaded vector data using control data that specifies which elements to extract. This extraction process automatically excludes invalid or padding information, ensuring that only valid data is processed while maintaining full register utilization for subsequent operations.

Inventive Principle:
Principle #2Taking out (Extraction)

3Manufacturing precision

If splicing instruction is used to extract data elements from vector register, then data alignment and validity are improved, but instruction complexity increases

Engineering Contradiction:
Improvedata alignmentVSAvoidinstruction complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent performs preliminary action by pre-calculating and storing the control data that identifies which data elements to extract in a control register before executing the splicing instruction. This preparation step simplifies the actual splicing operation, as the instruction only needs to read the pre-computed control data and perform the extraction, rather than computing the element selection on the fly.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentEP3953808B1Method and apparatus for processing data splicing instruction
Publication Date: 2025.09.17 C SKY MICROSYST CO LTD
  • EP3953808B1 patent drawingFigure 1
  • EP3953808B1 patent drawingFigure 2
  • EP3953808B1 patent drawingFigure 3

AI summary

The present disclosure discloses an instruction processing apparatus, comprising a first vector register adapted to store a first, vector to be operated on, a second vector register adapted to store a second vector to be operated on, a decoder adapted to receive and decode a data splicing instruction, and an execution unit The data splicing instruction indicates the first vector register as a first operand, the second vector register as a second operand, a splicing indicator, and a destination. The execution unit is coupled to the first vector register, the second vector register, and the decoder, and is adapted to execute the decoded data splicing instruction, so as to acquire a.first part of the first vector from the first vector register and acquire a second part of the second vector from the second vector register according to the splicing indicator, splice the acquired first part of the first vector and the acquired second part of the second vector to form a third vector, and store the third vector into the destination.