Vector Element Selection Unit Using Layered Multiplexers
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Solution Overview
Problem
Current digital signal processing systems face inefficiencies in data element selection and aggregation, particularly in LTE communication systems, due to high processor load and latency caused by coarse-grained data transfer and complex control structures, which hinder the performance of vector operations.
Innovation Solution
An element selection unit with a selector control circuit and a selector data path circuit comprising multiple layers of multiplexers, where multiplexer control signals are generated based on a bit map and relative offset values, enabling efficient selection and aggregation of data elements from input vectors into output vectors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a scalar DSP is used for data element selection, then selectivity is improved, but processor load and latency increase significantly
Solution Approach 1:
The patent replaces the mechanical scalar processing approach with a vector processing system that uses parallel hardware structures (multiplexers arranged in layers) to perform data element selection. This substitution of mechanical sequential operations with parallel vector operations resolves the contradiction by achieving both selectivity and high productivity simultaneously.
Solution Approach 2:
The patent segments the data processing into multiple layers of multiplexers, where each layer handles specific routing decisions. This segmentation allows the system to maintain scalar-level selectivity control while achieving vector-level throughput by processing multiple data elements through different multiplexer layers in parallel.
2Productivity
If DMA units are used for data transport, then data transfer capability is improved, but fine-grained selection capability is lost
Solution Approach 1:
The patent merges the data transfer function (typically handled by DMA) with the data selection function (typically handled by scalar processors) into a single integrated element selection unit. This merging allows the system to achieve both high data transfer capability and fine-grained selection capability by selecting and transferring data elements in the same operational stage using vector operations.
Solution Approach 2:
The element selection unit is designed as a universal structure that can handle both data transfer and data selection tasks simultaneously. The layered multiplexer architecture provides multi-functionality, allowing the same hardware structure to perform coarse-grained data movement and fine-grained element selection without requiring separate specialized units.
3Adaptability or versatility
If shuffle-based systems are used for element selection, then selection flexibility is improved, but area and power consumption increase
Solution Approach 1:
The patent implements a dynamic control mechanism where the selection pattern is determined by runtime parameters (source index, destination index, and bitmap) rather than fixed hardware interconnect patterns. This dynamic approach provides selection flexibility comparable to shuffle-based systems while using a more area-efficient layered multiplexer structure that can be controlled through software parameters.
Data Source
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Figure 3
AI summary
An element selection unit (200) and a method therein for vector element selection. The element selection unit comprises a selector control circuit (404) and a selector data path circuit (406), which data path circuit comprises a plurality of layers of multiplexers. The element selection unit further comprises a receiving circuit (401) configured to receive an instruction to perform a selection of elements from an input vector. The selector control circuit (404) is configured to generate a multiplexer control signal for each multiplexer based on a bit map and on a plurality of relative offset values. The data path circuit is configured to propagate the elements comprised in the input vector through the plurality of layers of multiplexers towards an output vector based on the generated multiplexer control signals. The data path circuit is further configured to write the propagated elements to enabled elements of the output vector.