Vector-Feedback Frequency Synthesizer for Wideband Low-Noise Tuning
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Solution Overview
Problem
Conventional frequency synthesizers face challenges in finely setting frequencies over a broad band with low noise and broad frequency entrainment range, and suffer from increased noise due to simultaneous switching in digital/analog converters.
Innovation Solution
A novel frequency synthesizer architecture that includes a voltage-controlled oscillation unit, frequency division, analog/digital conversion, vector extraction, and feedback mechanisms to adjust the frequency signal, using orthogonal detection and integrating circuits to control the voltage-controlled oscillator, allowing for precise frequency setting and noise reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the frequency division ratio N is increased to set frequency finely, then frequency resolution is improved, but noise becomes large due to elongation of delay in loop
Solution Approach 1:
The frequency setting range is divided into multiple bands, with each band having its own PLL circuit optimized for that range. This segmentation allows each PLL to operate with appropriate frequency division ratios, avoiding the noise issues that would result from using an excessively high division ratio across the entire frequency range.
Solution Approach 2:
The system dynamically switches between different PLL circuits based on the desired output frequency. The control unit selects which PLL circuit to use depending on the target frequency, ensuring optimal operation in each frequency band and maintaining low noise while achieving fine frequency resolution.
2Adaptability or versatility
If multistage frequency synthesizers are combined to extend frequency range, then frequency coverage is improved, but circuit construction becomes complicated and noise is increased
Solution Approach 1:
Each PLL circuit is designed to be multi-functional, capable of operating across different frequency bands by adjusting its frequency division ratio. This universality allows a single PLL circuit to replace multiple specialized circuits, reducing overall system complexity while maintaining broad frequency coverage.
Solution Approach 2:
The system uses dynamic switching between different PLL circuits based on the required frequency band. The control unit determines which PLL circuit is most suitable for the target frequency and activates only that circuit, avoiding the complexity of having all circuits operating simultaneously and reducing overall noise.
3Measurement precision
If the frequency division ratio N is increased to set frequency finely, then frequency resolution is improved, but the upper limit of N is equal to about 1000 due to noise
Solution Approach 1:
The frequency range is segmented into multiple bands, each handled by a dedicated PLL circuit. This allows each circuit to use an optimized frequency division ratio appropriate for its band, achieving fine frequency resolution without requiring excessively high division ratios that would compromise reliability.
Solution Approach 2:
The control unit monitors the operating conditions and dynamically selects the most appropriate PLL circuit based on the desired frequency and current system state. This feedback mechanism ensures that the system always operates within reliable parameters while maintaining fine frequency resolution.
Data Source
AI summary
An object of the present invention provides a frequency synthesizer having a broad frequency entraining range which can finely set a frequency over a broad band by a novel principle.As s specific solving means, a sinusoidal signal of an output frequency of a voltage-controlled oscillator is subjected to orthogonal detection, a vector rotating at the differential frequency (speed) between the output frequency and the frequency of the frequency signal used for the detection is created, and the frequency of a vector when the output frequency of the voltage-controlled oscillator is equal to a set value is calculated in advance. The voltage signal corresponding to the difference between the frequency of the vector and the calculated frequency is fed back to the voltage-controlled oscillator when the voltage-controlled oscillator is driven, and PLL is formed so that the difference is equal to zero. Accordingly, the output frequency of the voltage-controlled oscillator is adjusted to the set frequency when PLL is locked. After the difference between both the frequencies is increased after PLL is locked, the set value is integrated by the integrating circuit portion and added to the control voltage.