Vector Fetch Bus Error Handling in Computer Processors
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Solution Overview
Problem
Current computer processing systems face catastrophic errors when a bus error occurs during an exception vector fetch, leading to continuous error processes or 'hang' situations, necessitating improved error handling mechanisms.
Innovation Solution
The system recognizes a vector fetch bus error, sets a vector fail status flag, and substitutes the failed exception vector with a 'vector fail address' pointing to a vector fetch bus error handler to handle the error, allowing for execution of a dedicated or existing bus error handler to recover from the error.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the processor reads the exception vector from the vector table during exception handling, then the exception handler can be executed, but a bus error during the vector fetch causes catastrophic system failure
Solution Approach 1:
The system prepares alternative exception vectors in advance (stored in reserved memory locations) that can be used as fallbacks when the primary exception vector becomes inaccessible due to bus errors. This pre-prepared cushioning mechanism prevents catastrophic failure by having backup recovery paths ready before errors occur.
Solution Approach 2:
An intermediary mechanism is introduced between the processor and the exception vector table access. This intermediary monitors bus errors during vector fetch operations and intercepts catastrophic failures, allowing the system to switch to alternative exception handlers rather than crashing directly.
2Ease of operation
If the processor enters continuous error processing upon bus error, then error handling is initiated, but the system hangs and cannot recover
Solution Approach 1:
The system performs preliminary actions by pre-configuring alternative exception vectors and establishing error detection mechanisms before bus errors occur. When errors happen, the pre-established recovery paths enable immediate switching without entering hang states, maintaining system productivity.
Solution Approach 2:
A feedback mechanism is implemented that monitors the status of exception vector access and provides real-time information about bus errors. This feedback loop allows the system to detect errors early and switch to alternative handlers, preventing continuous error processing and hang conditions.
3Quantity of substance
If a single exception vector table is used, then memory space is conserved, but error recovery options are limited
Solution Approach 1:
The system implements multi-functionality by using reserved memory locations to serve dual purposes: normal memory operations and storage of alternative exception vectors. This allows the same memory space to provide both conventional functionality and enhanced error recovery capabilities, maintaining memory efficiency while increasing adaptability.
Solution Approach 2:
The system changes the parameter of exception vector storage by utilizing reserved memory locations that can be dynamically configured to hold alternative exception vectors. This parameter change enables the system to switch between different exception handling modes without requiring separate dedicated memory spaces, balancing memory usage and recovery options.
Data Source
AI summary
A computer system includes a non-transitory computer-readable memory to store (a) a vector table including an exception vector pointing to an exception handler and (b) a vector fail address of a vector fetch bus error handler, and a processor to identify an exception, initiate an exception vector fetch in response to the identified exception to read the exception vector from the vector table, identify a vector fetch bus error associated with the exception vector fetch, access the vector fail address of the vector fetch bus error handler in response to the vector fetch bus error, and execute the vector fetch bus error handler.