Vector FIR Filtering with Data Reordering for Real-Time DSP
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Solution Overview
Problem
Digital signal processors face challenges in efficiently processing real-time data streams due to limitations in memory bandwidth and scheduling, particularly in applications requiring predictable non-sequential input patterns.
Innovation Solution
The implementation of a streaming engine within the DSP core that includes address generation, data formatting, and storage for formatted data, along with instruction support for vector-based finite impulse response (FIR) filtering, vector and scalar multiplication, and matrix multiplication, enhances memory bandwidth and data scheduling by managing multiple data streams and performing operations critical for computer vision processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional memory access methods are used to load data registers, then memory bandwidth is limited and cache miss stalls increase, but processing speed and real-time performance deteriorate
Solution Approach 1:
The patent implements a data register file that pre-loads and caches frequently accessed data elements before they are needed for filtering operations. The system anticipates data access patterns and prepares data in advance, reducing cache miss stalls during actual processing. This preliminary action allows the processor to maintain high processing speed without waiting for memory bandwidth limitations.
2Productivity
If scalar operations are used for FIR filtering, then implementation is simple, but processing efficiency and productivity are low
Solution Approach 1:
The patent merges multiple scalar FIR filtering operations into a single vector instruction that processes multiple data elements simultaneously. The vector FIR filter instruction combines several filtering operations that would traditionally require separate scalar instructions, thereby increasing productivity without requiring proportionally more complex hardware. The data register file and vector multiplier work together to execute these combined operations efficiently.
3Adaptability or versatility
If non-sequential input data patterns are processed, then application flexibility is improved, but memory scheduling complexity and access time increase
Solution Approach 1:
The patent introduces a data register file as an intermediary between main memory and the filtering units. This intermediary structure buffers data elements and reorganizes them according to the required access patterns, whether sequential or non-sequential. By decoupling the memory access pattern from the processing requirements, the system achieves flexibility in handling various data patterns without incurring excessive memory access time penalties.
Data Source
AI summary
A method includes executing, by a processor a vector finite impulse response (VFIR) filter instruction that specifies coefficients, data elements, and a storage location. The executing includes reordering a subset of the data elements to provide each data element of the reordered subset of the data elements to a respective slice multiply component of a vector multiplier of the processor, generating, by the vector multiplier, filter outputs based on the coefficients and data elements, and storing the filter outputs in the storage location.