Vector FIR Filtering With Streaming Engine Memory Scheduling
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Solution Overview
Problem
Digital signal processors face challenges in efficiently processing real-time data streams due to limitations in memory bandwidth and scheduling, particularly in applications requiring predictable non-sequential input patterns for video encoding and other data processing tasks.
Innovation Solution
The implementation of a streaming engine within the DSP core that manages data streams by generating addresses, performing data formatting, and optimizing memory access, allowing for improved memory bandwidth and reduced cache miss stalls, thereby enhancing data scheduling and processing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional memory access methods are used in DSP processors, then memory bandwidth is limited and cache miss stalls occur, but processing efficiency and real-time performance deteriorate
Solution Approach 1:
The streaming engine performs preliminary actions by pre-fetching data from memory into an input buffer before the DSP core needs it, and pre-computing output addresses using address generation logic. This preliminary data preparation and address computation eliminates cache miss stalls during actual processing, as the data is already available in the output buffer when needed.
Solution Approach 2:
The streaming engine acts as an intermediary between memory and the DSP core. It includes an input buffer that receives data from memory, an output buffer that supplies data to the DSP core, and address generation logic that mediates the address computation. This intermediary structure decouples the memory access timing from the processing timing, allowing the DSP core to process data without waiting for memory operations.
2Productivity
If scalar operations are used for FIR filtering, then implementation is simple, but the number of operations required is large and processing speed is slow
Solution Approach 1:
The streaming engine merges multiple scalar operations into unified vector operations. The address generation logic computes multiple output addresses simultaneously using the same input address and filter coefficient information. The buffering structure enables batch processing of multiple data elements through the DSP core, reducing the total number of individual operations required for FIR filtering.
Solution Approach 2:
The invention transitions from scalar processing to vector processing by introducing buffers that hold multiple data elements and address generation logic that computes multiple addresses in parallel. This dimensional change from scalar to vector operations allows the system to process multiple filter coefficients and data elements simultaneously, dramatically increasing filtering speed.
3Adaptability or versatility
If sequential data access patterns are used, then memory access is simple, but video encoding applications requiring non-sequential access cannot be efficiently processed
Solution Approach 1:
The address generation logic acts as an intermediary that handles complex non-sequential memory access patterns. It computes output addresses based on input addresses and filter coefficients, enabling the system to access memory in non-sequential patterns required by video encoding applications. This intermediary logic absorbs the complexity of non-sequential access, leaving the rest of the system simple.
Solution Approach 2:
The streaming engine changes the parameter of data access by introducing buffering. Data is fetched from memory in one pattern (controlled by address generation logic), stored in buffers, and then supplied to the DSP core in a different pattern. This parameter change in data access timing and pattern enables support for video encoding applications while keeping the memory interface relatively simple.
Data Source
AI summary
A method is provided that includes performing, by a processor in response to a vector finite impulse response (VFIR) filter instruction, generating of a plurality of filter outputs using a plurality of coefficients and a plurality of sequential data elements, the plurality of coefficients specified by a coefficient operand of the VFIR filter instruction and the plurality of sequential data elements specified by a data operand of the VFIR filter instruction, and storing the filter outputs in a storage location specified by the VFIR filter instruction.