Vector Floating Point Argument Reduction for Overflow Prevention

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Solution Overview

Problem

Vector normalisation in data processing systems using floating-point arithmetic often results in overflow or underflow issues due to limited precision, leading to loss of precision and increased power consumption when attempting to address these problems with higher precision calculations or additional divisions.

Innovation Solution

The introduction of an argument reduction instruction that scales vector components by adjusting exponent values to keep the largest component within a safe range, preventing overflow or underflow, and allowing for efficient processing with minimal circuit and power overhead, while handling special cases like NaN and infinity values.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If intermediate calculations are performed with higher precision (e.g., double-precision for single-precision input), then precision is improved and overflow/underflow is avoided, but processing speed decreases and power consumption increases

Engineering Contradiction:
Improvecalculation precisionVSAvoidprocessing speed
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

The patent changes the exponent parameter of floating-point numbers by adding an offset value to shift the range of representable values. This allows intermediate calculations to remain within the original precision format while avoiding overflow and underflow conditions, thereby maintaining both precision and processing speed without requiring higher precision arithmetic operations

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If vector components are divided by the largest component value to normalize, then precision is improved, but additional floating-point divisions increase power consumption and reduce processing speed

Engineering Contradiction:
Improvenormalisation precisionVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

Instead of performing division operations, the patent modifies the exponent parameter of the floating-point representation. By adding an offset to the exponent, the normalization is achieved through parameter transformation rather than arithmetic division, significantly reducing power consumption while maintaining precision

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent replaces the mechanical division operation with a simpler exponent addition operation. This substitution transforms a complex arithmetic operation into a simpler parameter manipulation, reducing both power consumption and computational complexity while achieving the same normalization effect

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Productivity

If the dot-product is calculated directly without argument reduction, then processing speed is maintained, but overflow or underflow occurs resulting in loss of precision

Engineering Contradiction:
Improveprocessing speedVSAvoidcalculation reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies argument reduction as a preliminary action before calculating the dot-product. By adjusting the exponent parameters of input vectors beforehand, the patent ensures that subsequent calculations will not overflow or underflow, maintaining both speed and reliability

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The exponent offset acts as an intermediary that mediates between the input values and the dot-product calculation. This intermediary transformation ensures that the calculation proceeds within safe numerical bounds without requiring higher precision or additional normalization steps

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS9146901B2Vector floating point argument reduction
Publication Date: 2015.09.29 ARM LTD
  • US9146901B2 patent drawing
  • US9146901B2 patent drawing
  • US9146901B2 patent drawing

AI summary

A processing apparatus is provided with processing circuitry 6, 8 and decoder circuitry 10 responsive to a received argument reduction instruction FREDUCE4, FDOT3R to generate control signals 16 for controlling the processing circuitry 6, 8. The action of the argument reduction instruction is to subject each component of an input vector to a scaling which adds or subtracts an exponent shift value C to the exponent of the input vector component. The exponent shift value C is selected such that a sum of this exponent shift value C with the maximum exponent value B of any of the input vector components lies within a range between a first predetermined value and a second predetermined value. A consequence of execution of this argument reduction instruction is that the result vector when subject to a dot-product operation will be resistant to floating point underflows or overflows.