Vector Floating-Point Classification for DSPs

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Solution Overview

Problem

Modern digital signal processors (DSPs) face challenges in efficiently emulating floating-point operations, particularly in handling special floating-point values like zero, subnormal, infinity, and NaN values, which require multiple instructions to classify correctly, leading to increased instruction and computational overhead.

Innovation Solution

A vector floating-point classification instruction is introduced, which classifies multiple floating-point values in a single instruction, reducing overhead by quickly identifying special floating-point values and storing their classifications in a destination register, allowing for efficient handling in vectorized operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If multiple instructions are used to extract and test fields from floating-point values, then classification accuracy is improved, but instruction overhead and computational time increase

Engineering Contradiction:
Improvefloating-point value classification accuracyVSAvoidinstruction overhead time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent combines multiple classification operations into a single vector instruction that processes multiple floating-point values simultaneously. The functional unit extracts fields and performs classification tests in parallel across multiple data elements, reducing the total instruction count while maintaining accurate classification of special floating-point values including zeros, subnormals, infinities, and NaNs.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The vector classification functional unit performs multiple functions within a single instruction execution: it extracts exponent and fraction fields, compares values against threshold criteria, identifies special floating-point categories, and stores classification results. This multi-functional approach eliminates the need for separate instructions for each classification step.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If scalar instructions are used to classify floating-point values, then implementation simplicity is maintained, but processing speed decreases

Engineering Contradiction:
Improvefloating-point classification speedVSAvoidinstruction set complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent segments the floating-point classification task into parallel operations that can be executed simultaneously across multiple data elements. By dividing the classification work into independent lane operations within the vector register, the system achieves parallel processing without requiring complex inter-element coordination, thus improving speed while keeping the instruction architecture relatively simple.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention transitions from scalar processing (one value at a time) to vector processing (multiple values simultaneously). This dimensional expansion from 1D scalar operations to multi-element parallel operations enables significant throughput improvement while the functional unit remains a single integrated component, avoiding the complexity of multiple separate scalar functional units.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20250053420A1Vector floating-point classification
Publication Date: 2025.02.13 TEXAS INSTRUMENTS INC
  • US20250053420A1 patent drawing
  • US20250053420A1 patent drawing
  • US20250053420A1 patent drawing

AI summary

Systems and methods enable the classification of each value of multiple floating-point values stored in a first vector register, and storage in a second vector register multiple elements that each indicate a respective classification of a respective value of the multiple floating-point values. A system includes a functional unit, first and second vector registers coupled to the functional unit, and processing circuitry. The processing circuitry is configurable, e.g., via an instruction, to cause the functional unit to perform the classification and storage operations.