Vector Gather Scatter Security via Capability Segmentation
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Solution Overview
Problem
Existing vector processing systems struggle to execute vector gather or vector scatter instructions while ensuring security benefits through the use of capabilities, as capabilities that provide address indications are inherently larger due to constraining information.
Innovation Solution
The system employs processing circuitry, vector registers, and an instruction decoder to decode vector instructions. It determines the necessary vector registers for data elements and capabilities, uses capabilities to generate memory addresses, and enforces constraining information to allow or deny memory access operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If capabilities are used to provide address indications for vector gather or scatter instructions, then security benefits are achieved, but the size of the address indication increases due to constraining information
Solution Approach 1:
The capability structure is segmented into distinct fields: an address indication field and a constraining information field. This segmentation allows the system to separately handle the address specification and security constraints, enabling efficient processing where the address indication can be extracted and used for memory access while the constraining information is independently evaluated for security validation.
Solution Approach 2:
The address indication is extracted from the capability structure and used specifically for determining memory addresses in vector gather or scatter operations. This extraction allows the address component to be utilized independently from the constraining information, which remains in the capability structure for security validation purposes only.
2Reliability
If multiple vector registers are allocated to store capabilities for each data element, then security validation is enabled, but the number of vector registers increases beyond what is needed for data storage
Solution Approach 1:
Vector registers are given multi-functionality by allowing them to store both data elements and capabilities. The same vector register file is used for both purposes, with the distinction being made through the instruction decoding process that identifies whether a vector register contains data or capabilities based on the instruction type and register numbering conventions.
Solution Approach 2:
The system adds a functional dimension to vector register usage by introducing capability vector indication fields that operate in parallel with data vector indication fields. This allows the system to track and manage capabilities associated with each data element without requiring separate physical register files, effectively adding a logical layer of capability management.
3Reliability
If vector gather or scatter instructions are executed with capabilities, then secure memory access is achieved, but the instruction decoding and execution complexity increases
Solution Approach 1:
The instruction decoder is designed with specialized handling for capability-related fields specifically in vector gather or scatter instructions. Rather than uniformly processing all vector instructions, the decoder applies localized processing logic that identifies capability vector indication fields and routes them through appropriate validation paths, maintaining efficiency for standard instructions while providing enhanced security processing when needed.
Solution Approach 2:
The system performs preliminary identification of capability vector indication fields during instruction decoding, before the actual memory access operations are executed. This preliminary action allows the decoder to prepare the necessary validation context and retrieve the appropriate capabilities from vector registers in advance, streamlining the subsequent security validation and memory access execution.
Data Source
AI summary
An apparatus is described having processing circuitry to perform vector processing operations, a set of vector registers, and an instruction decoder to decode vector instructions to control the processing circuitry to perform the required operations. The instruction decoder is responsive to a given vector memory access instruction specifying a plurality of memory access operations, where each memory access operation is to be performed to access an associated data element, to determine, from a data vector indication field of the given vector memory access instruction, at least one vector register in the set of vector registers associated with a plurality of data elements, and to determine, from at least one capability vector indication field of the given vector memory access instruction, a plurality of vector registers in the set of vector registers containing a plurality of capabilities. Each capability is associated with one of the data elements in the plurality of data elements and provides an address indication and constraining information constraining use of that address indication when accessing memory. The number of vector registers determined from the at least one capability vector indication field is greater than the number of vector registers determined from the data vector indication field. The instruction decoder controls the processing circuitry: to determine, for each given data element in the plurality of data elements, a memory address based on the address indication provided by the associated capability, and to determine whether the memory access operation to be used to access the given data element is allowed in respect of that determined memory address having regard to the constraining information of the associated capability; and to enable performance of the memory access operation for each data element for which the memory access operation is allowed.