Vector Processor Gather Scatter Ports
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Solution Overview
Problem
Traditional gather/scatter operations in vector processors are complex and slow, unable to keep up with the high data access rates of vector processors, particularly when dealing with non-contiguous data, which limits the processing speed of vector and matrix operations.
Innovation Solution
A vector processor apparatus with multiple vector ports and a random access memory (RAM), where each port uses an address register and a stride register to communicate with the RAM, enabling efficient non-contiguous data gathering and scattering, supporting up to 2 reads and 1 write per clock cycle, and allowing for parallelization to enhance processing speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional gather/scatter operations are used in vector processors, then general purpose processing is maintained, but processing speed deteriorates due to complexity and inability to handle non-contiguous data efficiently
Solution Approach 1:
The memory interface is segmented into multiple independent vector ports (at least two ports), each capable of handling vector operations autonomously. This segmentation allows parallel processing of multiple vectors simultaneously, thereby increasing productivity while maintaining manageable complexity through modular design.
Solution Approach 2:
The patent introduces a new dimension of parallelism by adding multiple vector ports that can operate concurrently. This dimensional expansion from single-port to multi-port architecture enables simultaneous gather/scatter operations on different vectors, resolving the speed-complexity contradiction through increased operational throughput.
2Adaptability or versatility
If non-contiguous data is accessed in vector processors, then data flexibility is improved, but processing speed deteriorates due to inability to maintain high data access rates
Solution Approach 1:
Address registers and stride registers are pre-configured with starting addresses and increment values before vector operations begin. This preliminary setup allows the memory interface to automatically generate sequential addresses for non-contiguous data elements without complex runtime calculations, maintaining high data access rates while handling flexible memory patterns.
Solution Approach 2:
Address registers and stride registers act as intermediaries between the control logic and memory interface. These registers pre-compute and store address sequences, mediating the complexity of non-contiguous address generation and allowing the memory interface to operate at full speed with simple sequential address increments.
3Speed
If multiple vector ports are added to handle non-contiguous data efficiently, then data access speed is improved, but device complexity increases
Solution Approach 1:
Each vector port is designed as a universal interface that can handle both contiguous and non-contiguous data access patterns using the same address register and stride register mechanism. This multi-functionality reduces overall device complexity by avoiding the need for separate specialized circuits for different access patterns.
Solution Approach 2:
The patent uses parameter-based control where stride registers store increment values that can be changed to adapt to different memory access patterns. By changing the stride parameter rather than reconfiguring the hardware architecture, the system maintains simplicity while achieving high-speed access to various data layouts.
Data Source
AI summary
In one implementation a vector processor gather/scatter apparatus comprises a plurality of vector ports, and a random access memory, where the plurality of vector ports are in communication with the random access memory, and where one or more of the plurality of vector ports uses one or more of an address register and one or more of a stride register in communication with the random access memory to allow the gather/scatter of random access memory contents.