Vector Generating Instruction Circular Addressing
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Solution Overview
Problem
In vector processing systems, supporting circular addressing modes efficiently is challenging due to the need for additional logic in the memory access path, which can hinder processing efficiency and increase timing constraints.
Innovation Solution
A vector generating instruction that identifies a scalar start value and wrapping control information is used to generate a vector of elements, allowing circular addressing within memory without requiring additional logic in the memory access path, enabling flexible use of circular buffers and efficient memory access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If additional logic is added to the memory access path to support circular addressing modes, then circular addressing functionality is enabled, but processing efficiency decreases and timing constraints increase
Solution Approach 1:
The patent extracts the circular addressing logic from the memory access path and relocates it to the vector register file. Specifically, the vector generating instruction implemented in the vector functional unit creates vectors with wrapping values that directly encode circular addressing information, eliminating the need for additional logic in the memory access path while maintaining circular addressing functionality.
Solution Approach 2:
The patent introduces a vector as an intermediary data structure that carries circular addressing information. The vector generating instruction creates a vector where elements wrap around based on a specified width, and this vector is then used by subsequent memory access instructions to perform circular addressing without requiring the memory access path to understand circular addressing semantics.
2Adaptability or versatility
If additional logic is added to the memory access path to support circular addressing modes, then circular addressing functionality is enabled, but timing constraints increase
Solution Approach 1:
The patent performs preliminary action by pre-generating vectors with wrapping values using the vector generating instruction before the memory access occurs. The vector functional unit creates vectors where the wrapping behavior is pre-computed, allowing the memory access path to simply use these pre-prepared vectors without needing to perform additional timing-critical wrapping calculations during the memory access itself.
3Adaptability or versatility
If vector registers are used to store vectors for circular addressing, then flexible buffer sizes and locations are enabled, but the scarce vector register resources are consumed
Solution Approach 1:
The patent changes the parameter of vector width to enable flexible buffer sizes. The vector generating instruction accepts a vector width parameter that determines the wrap-around point, allowing the same vector register to be configured for different buffer sizes by simply changing the width parameter rather than requiring different physical registers for different buffer configurations.
Data Source
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AI summary
An apparatus and method are provided for performing vector processing operations. In particular the apparatus has processing circuitry to perform the vector processing operations and an instruction decoder to decode vector instructions to control the processing circuitry to perform the vector processing operations specified by the vector instructions. The instruction decoder is responsive to a vector generating instruction identifying a scalar start value and wrapping control information, to control the processing circuitry to generate a vector comprising a plurality of elements. In particular, the processing circuitry is arranged to generate the vector such that the first element in the plurality is dependent on the scalar start value, and the values of the plurality of elements follow a regularly progressing sequence that is constrained to wrap as required to ensure that each value is within bounds determined from the wrapping control information. The vector generating instruction can be useful in a variety of situations, a particular use case being to implement a circular addressing mode within memory, where the vector generating instruction can be coupled with an associated vector memory access instruction. Such an approach can remove the need to provide additional logic within the memory access path to support such circular addressing.