Vector Load-Store Handshaking for Safe Out-of-Order Micro-Ops

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Solution Overview

Problem

Existing vector processing units (VPUs) face challenges in efficiently executing load-store instructions due to the complexity of handling micro-operations that may generate exceptions, leading to potential software-observable side effects and security vulnerabilities, especially when micro-operations are executed out-of-order.

Innovation Solution

A handshaking protocol is implemented between the control unit, vector processing unit (VPU), and load-store unit (LSU) to ensure that micro-operations are only executed after receiving an allow signal, and exceptions are properly handled to prevent architectural updates until it is safe to do so, using instruction and micro-operation identifiers for coordination.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If micro-operations are executed out-of-order to improve performance, then productivity is improved, but reliability deteriorates due to potential software-observable side effects and security vulnerabilities

Engineering Contradiction:
Improveinstruction execution speedVSAvoidexception handling safety
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The system performs preliminary actions by sending allow signals to the VPU before micro-operations are executed. The control unit determines whether conditions are met (no pending exceptions, architectural state is safe) and issues allow signals in advance, enabling the VPU to prepare and execute micro-operations out-of-order while maintaining reliability guarantees.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system implements feedback mechanisms where the LSU reports exception status back to the control unit, and the control unit adjusts allow signal issuance accordingly. This feedback loop ensures that out-of-order execution does not compromise reliability, as the system continuously monitors and responds to exception conditions.

Inventive Principle:
Principle #23Feedback

2Reliability

If dedicated logic is added to track micro-op order and exceptions, then reliability is improved, but device complexity increases

Engineering Contradiction:
Improvemicro-op execution safetyVSAvoidpipeline logic complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The VPU acts as an intermediary between the control unit and LSU, managing the complexity of tracking micro-op order and exception status. The VPU receives allow signals, manages its internal queue of micro-operations, and coordinates with the LSU, thereby isolating the complexity from the control unit and LSU while maintaining reliability.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The system segments the execution pipeline into distinct functional units: the control unit for high-level decision-making, the VPU for micro-op management and queuing, and the LSU for memory operations. This segmentation distributes complexity across multiple components, making the overall system more manageable while maintaining reliability through clear separation of concerns.

Inventive Principle:
Principle #1Segmentation

3Reliability

If the LSU checks exception status for each micro-op, then reliability is improved, but productivity decreases due to additional checking overhead

Engineering Contradiction:
Improveexception detection accuracyVSAvoidmicro-op execution throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system extracts exception detection and status tracking from the LSU and places it in the VPU. The VPU maintains exception status information and uses it to control the issuance of allow signals, thereby relieving the LSU of the burden of checking exception status for each micro-op while maintaining reliable exception detection.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentEP4708037A1Processing vector instructions
Publication Date: 2026.03.11 IMAGINATION TECH LTD
  • EP4708037A1 patent drawingFigure 1
  • EP4708037A1 patent drawingFigure 2
  • EP4708037A1 patent drawingFigure 3

AI summary

A handshaking protocol is implemented between a control unit, a vector processing unit (VPU) and a load-store unit (LSU). Micro-ops of an instruction will only be executed by the LSU if it is guaranteed not to generate an exception and no earlier micro-ops will generate an exception. The handshaking protocol guarantees this using signals passed between the control unit, VPU and LSU. To be accompanied, when published, by Figure 2 of the accompanying drawings.