Vector Index Registers for Faster Non-Sequential Vector Access
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Solution Overview
Problem
Conventional scalar index registers in vector processors require continual changing of values during operations, leading to performance curbs when accessing multiple positions of operand vectors, as each incrementation needs to be separately loaded.
Innovation Solution
Implementing vector index registers (VIRs) that store multiple addresses for accessing non-sequential elements in vectors, allowing operations to move through elements i_1, i_2, ..., i_n, and loading each address only once, thereby replacing the need for continual scalar index register changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If scalar index registers are used for accessing multiple positions in operand vectors, then the processor can perform indexing operations, but each incrementation needs to be separately loaded which curbs performance
Solution Approach 1:
The patent divides the index register into multiple segments or fields within a single register structure. Instead of using one scalar register that must be incremented sequentially, the index register is segmented to allow parallel or simultaneous access to multiple index values, thereby reducing the time needed for sequential loading and incrementation operations.
Solution Approach 2:
The patent transitions from a one-dimensional scalar index register to a multi-dimensional index register structure that can store multiple index values simultaneously. This dimensional expansion allows the processor to access multiple positions in operand vectors without sequential incrementation, effectively adding a new dimension to the indexing capability.
2Adaptability or versatility
If scalar index registers are used for indexing operations, then the processor can modify operand addresses, but continual changing of register values increases power consumption
Solution Approach 1:
The patent pre-loads multiple index values into the index register simultaneously before the indexing operation begins. By performing the loading action in advance and in parallel rather than sequentially during execution, the processor reduces the total number of write operations required, thereby reducing power consumption while maintaining full indexing capability.
Solution Approach 2:
The patent combines multiple scalar index register operations into a single multi-field index register. By merging the functionality of multiple sequential scalar registers into one unified structure that can hold and process multiple index values simultaneously, the system reduces the total operational overhead and associated power consumption.
3Ease of operation
If conventional scalar registers are used for indexing, then the processor can access vectors, but the device complexity increases due to continual loading and incrementation
Solution Approach 1:
The patent designs the index register with multi-field structure that serves multiple functions simultaneously: it can store base addresses, offset values, and stride information all in one register. This universal index register structure eliminates the need for separate scalar registers for different indexing purposes, reducing operational complexity while maintaining ease of vector access.
Data Source
AI summary
Disclosed herein are vector index registers for storing or loading indexes of true and/or false results of conditional operations in vector processors. Each of the vector index registers store multiple addresses for accessing multiple positions in operand vectors in various types of operations.