Vector Inner Product Computing Apparatus for Machine Learning Efficiency

The patent divides the vector inner product computation into multiple stages: a multiplication unit that computes partial products of vector elements, and an addition unit that accumulates these partial products. This segmentation allows parallel computation of multiple partial products simultaneously, improving execution efficiency while using a manageable number of hardware resources.

The patent introduces a hierarchical structure where the addition unit includes both a first adder for initial accumulation and a second adder for final summation, operating at different computational stages. This multi-dimensional approach to addition enables efficient handling of intermediate results and achieves high-speed computation with reduced hardware complexity.

The patent segments the computation into parallel multiplication operations followed by hierarchical addition. The multiplication unit can process multiple element pairs simultaneously, and the addition unit efficiently accumulates results in stages, achieving high computation speed without requiring a large number of adders that would increase hardware area.

The patent ensures continuous computation by having the multiplication unit continuously generate partial products that are immediately fed to the addition unit for accumulation. This continuous pipeline operation maintains high computation speed while using a compact, efficient hardware structure that minimizes arrangement area.