Vector Instruction Fusion for Processing Unit Execution Delay
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Solution Overview
Problem
In high-performance processing units, the execution delay between vector configuration and vector operation instructions leads to low efficiency due to the need for the vector operation instruction to wait for the completion of the vector configuration instruction, resulting in a significant delay and reduced processing efficiency.
Innovation Solution
A processing unit and method that fuse adjacent vector configuration and vector operation instructions into a single fusion instruction, allowing simultaneous execution by decoding the fusion instruction to obtain necessary execution information, modifying the vector control register, and bypassing the modified value to the vector operation unit, enabling concurrent execution without waiting for the configuration to complete.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the vector operation instruction waits for the vector configuration instruction to complete before execution, then the vector control register can be properly configured, but the execution delay increases and processing efficiency decreases
Solution Approach 1:
The patent merges the vector configuration instruction and vector operation instruction into a single fused instruction. The instruction decoding unit decodes the fused instruction to extract both configuration parameters (element width, element number, register grouping, rounding type) and operation parameters simultaneously. This allows the vector control register to be configured and the vector operation to be executed in the same clock cycle, eliminating the sequential waiting delay while ensuring proper configuration through the unified decoding process.
2Ease of operation
If the vector configuration instruction and vector operation instruction are executed sequentially, then the instruction execution order is simple to manage, but the execution delay between instructions increases
Solution Approach 1:
The patent combines configuration and operation instructions into one fused instruction that is decoded once to produce both configuration data and operation data. This maintains simplicity in instruction management at the software level while achieving parallel execution at the hardware level, thus reducing time loss without significantly complicating the execution management mechanism.
Solution Approach 2:
The instruction decoding unit performs preliminary decoding of the fused instruction to extract configuration parameters before the vector operation executes. The vector control register is configured in advance within the same clock cycle, so when the vector operation unit retrieves the configuration, it is already ready, eliminating the waiting delay.
3Reliability
If the vector operation instruction waits for configuration completion, then the configuration can take effect properly, but the overall instruction execution speed decreases
Solution Approach 1:
The fused instruction ensures that configuration and operation are tightly coupled in a single execution cycle. The decoding unit extracts configuration parameters and validates them simultaneously with operation parameters, ensuring the configuration takes effect properly before the operation uses it, all within the same clock cycle thereby maintaining high execution speed.
Data Source
AI summary
The embodiments of the present application provide a processing unit. The processing unit comprises: an instruction fetching unit configured for fusing instruction of vector configuration instruction and vector operation instruction that are adjacent in order to obtain fusion instruction; an instruction decoding unit configured to decode the fusion instruction to obtain first execution information and second execution information; a vector configuration unit configured to execute the vector configuration instruction according to the first execution information, modify vector control register, and bypass the value of the modified vector control register to the vector operation unit; the vector operation unit configured to execute the vector operation instruction according to the second execution information and the value of the modified vector control register.