Vector Instructions for Non-Maximum Suppression in Object Detection
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Solution Overview
Problem
Current methods for non-maximum suppression (NMS) in object detection, whether using CPUs or GPUs, face inefficiencies due to limited parallel computing capabilities and increased power consumption, leading to prolonged calculation times and high power usage.
Innovation Solution
A data processing method that utilizes specific instructions such as VRPAC, VIOU, VAADD, RPN_COR, and RPN_COR_DIAG to calculate and determine suppression vectors more efficiently, reducing the number of instructions and execution steps, and minimizing data loading times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If CPU is used for NMS calculation, then calculation can be performed, but calculation time is long due to limited parallel computing capability
Solution Approach 1:
The patent replaces traditional CPU-based sequential calculation with vector instruction-based parallel calculation. Specifically, it uses vector instructions (VRPAC, VIOU, VAADD) to perform parallel computation of proposal region areas and suppression matrices, substituting the mechanical sequential processing of CPU with a more efficient vectorized parallel processing approach that dramatically reduces calculation time.
Solution Approach 2:
The patent segments the NMS calculation process into distinct vectorizable operations: area calculation using VRPAC instruction, intersection-over-union calculation using VIOU instruction, and accumulation using VAADD instruction. This segmentation allows each operation to be optimized independently with appropriate vector instructions, improving overall calculation efficiency while maintaining correctness.
2Productivity
If GPU is used for NMS calculation, then parallel calculation capability is improved, but communication overhead between CPU and GPU increases calculation time and power consumption
Solution Approach 1:
The patent extracts the parallel calculation capability from GPU and brings it directly to the CPU through vector instruction support. By taking out the essential parallel processing function from the GPU architecture and implementing it natively in the CPU via vector instructions (VRPAC, VIOU, VAADD), the system eliminates the need for CPU-GPU data transfer and communication overhead, thereby reducing power consumption while maintaining parallel calculation advantages.
Solution Approach 2:
The patent introduces vector instructions as an intermediary mechanism that bridges the gap between CPU sequential processing limitations and GPU parallel processing advantages. These vector instructions act as a mediator that enables the CPU to perform parallel calculations efficiently without requiring actual GPU hardware or communication infrastructure, thus eliminating communication overhead while preserving parallel computation benefits.
3Measurement precision
If more instructions are invoked for NMS calculation, then calculation precision can be maintained, but instruction execution steps increase and time is prolonged
Solution Approach 1:
The patent merges multiple traditional calculation steps into single vector instructions. For example, the VRPAC instruction combines area calculation operations that would traditionally require multiple sequential instructions, while VIOU merges intersection and union calculations into one operation. This merging reduces the total number of instruction execution steps while maintaining calculation precision through the use of specialized vector operations designed to perform multiple functions simultaneously.
Data Source
AI summary
A data processing method and apparatus are disclosed. In various embodiments, R groups of proposal region sequences are obtained. Each group of proposal region sequence includes a plurality of proposal regions. In those embodiments, a VRPAC instruction is invoked to calculate an area of each proposal region in each group of proposal region sequence. For a jth group of proposal region sequence in the R groups of proposal region sequences, a VIOU instruction and a VAADD instruction are invoked to determine j suppression matrices of the jth group of proposal region sequence and determine a suppression vector of the jth group of proposal region sequence based on the j suppression matrices. In those embodiments, an unsuppressed proposal region is determined based on a suppression vector of each group of proposal region sequence.