Vector Processing Lane Masking Control Circuitry

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Solution Overview

Problem

Existing data processing apparatuses with multiple processing lanes often require explicit per-lane masking for vector processing operations, leading to increased control overhead and reduced performance.

Innovation Solution

A processing apparatus with decoder circuitry, processing circuitry having multiple lanes, and control circuitry that monitors each lane and modifies a per-lane mask based on predetermined conditions, allowing for dynamic enablement or disablement of processing lanes without explicit masking for each instruction.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If explicit per-lane masking is used for vector processing operations, then processing lane utilization can be controlled, but control overhead increases and performance decreases

Engineering Contradiction:

Improveprocessing lane utilization controlVSAvoidperformance

Core Design Contradiction:

Adaptability or versatilityVSProductivity

Solution Approach 1:

The processing apparatus automatically monitors its own processing state and dynamically modifies the per-lane mask based on saturation detection, eliminating the need for external explicit masking instructions. The system serves itself by autonomously optimizing lane utilization based on real-time processing conditions.

Inventive Principle:

Principle #25Self-service

Solution Approach 2:

The control circuitry continuously monitors the processing state of each lane and uses this feedback to dynamically adjust the per-lane mask. When saturation is detected in a lane, the system feedback-loops to modify the mask to disable that lane, creating a closed-loop control system that optimizes performance automatically.

Inventive Principle:

Principle #23Feedback

2Adaptability or versatility

If explicit per-lane masking is used for vector processing operations, then processing lane utilization can be controlled, but control overhead increases

Engineering Contradiction:

Improveprocessing lane utilization controlVSAvoidcontrol overhead

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

Inventive Principle:

Principle #25Self-service

Solution Approach 2:

The control circuitry combines the functions of monitoring processing state, detecting saturation, and modifying the per-lane mask into a single integrated control mechanism. This merging eliminates the need for separate explicit masking operations, reducing control overhead while maintaining adaptability.

Inventive Principle:

Principle #5Merging (Combining)

3Productivity

If all processing lanes are used for vector processing operations, then throughput is maximized, but energy consumption increases

Engineering Contradiction:

ImprovethroughputVSAvoidenergy consumption

Core Design Contradiction:

ProductivityVSUse of energy by moving object

Solution Approach 1:

The system dynamically adjusts the number of active processing lanes based on real-time saturation detection. Instead of statically using all lanes or a fixed subset, the per-lane mask is continuously modified to enable or disable lanes according to current processing conditions, optimizing the balance between throughput and energy consumption.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The system changes the operational parameters of processing lanes by dynamically modifying the per-lane mask. When saturation is detected, the mask parameter is changed to disable affected lanes, thereby reducing energy consumption while maintaining optimal throughput for the current workload.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS20250028530A1Techniques for controlling vector processing operations

Publication Date: 2025.01.23 ARM LTD

AI summary

There is provided a processing apparatus comprising decoder circuitry. The decoder circuitry is configured to generate control signals in response to an instruction. The processing apparatus further comprises processing circuitry which comprising a plurality of processing lanes. The processing circuitry is configured, in response to the control signals, to perform a vector processing operation in each processing lane of the plurality of processing lanes for which a per-lane mask indicates that processing for that processing lane is enabled. The processing apparatus further comprises control circuitry to monitor each processing lane of the plurality of processing lanes for each instruction of a plurality of instructions performed in the plurality of processing lanes and to modify the per-lane mask for a processing lane of the plurality of processing lanes in response to a processing state of the processing lane meeting one or more predetermined conditions.