Vector Lane Permutation Using Control Storage in DSPs
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Solution Overview
Problem
Digital signal processors face challenges in efficiently managing memory bandwidth and scheduling for real-time data processing, particularly in handling multiple data streams and performing vector permutations efficiently.
Innovation Solution
The implementation of a streaming engine within the DSP processor that includes two closely coupled streaming engines to manage data streams, along with instruction support for vector permutation, enabling all byte permute patterns and optimizing memory access through a system-on-chip architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional memory access methods are used for vector permutation, then memory bandwidth is limited, but processing speed and efficiency deteriorate
Solution Approach 1:
The processor is divided into multiple functional units including a permutation component that operates independently on vector data. This segmentation allows parallel processing of different vector elements, increasing throughput without proportionally increasing memory bandwidth requirements.
Solution Approach 2:
The patent introduces a control storage location dimension that stores permute control inputs separately from the data being processed. This additional dimension allows the permutation operation to be controlled without increasing the bandwidth of the data path, effectively adding control capability without proportional bandwidth cost.
2Adaptability or versatility
If complex vector permutation operations are implemented, then processing capability is improved, but device complexity increases
Solution Approach 1:
A control storage location acts as an intermediary between the permutation control inputs and the permutation component. This intermediary structure simplifies the control logic by providing a dedicated storage element that holds the permutation pattern, separating control from data processing and reducing overall system complexity.
Solution Approach 2:
The permutation component is designed to handle multiple permutation patterns through a single unified structure that accepts control inputs from the control storage location. This universal design allows the same hardware to perform various permutation operations without requiring separate dedicated circuits for each pattern.
3Measurement precision
If real-time data processing is performed with predictable non-sequential access patterns, then processing accuracy is improved, but memory access efficiency deteriorates
Solution Approach 1:
The control storage location pre-stores the permute control inputs that define the non-sequential access pattern. By having the permutation pattern prepared in advance in the control storage, the processor can execute the permutation operation immediately without real-time computation of access patterns, eliminating delays while maintaining the required non-sequential access behavior.
Data Source
AI summary
A method is provided that includes performing, by a processor in response to a vector permutation instruction, permutation of values stored in lanes of a vector to generate a permuted vector, wherein the permutation is responsive to a control storage location storing permute control input for each lane of the permuted vector, wherein the permute control input corresponding to each lane of the permuted vector indicates a value to be stored in the lane of the permuted vector, wherein the permute control input for at least one lane of the permuted vector indicates a value of a selected lane of the vector is to be stored in the at least one lane, and storing the permuted vector in a storage location indicated by an operand of the vector permutation instruction.