Vector Load Store Instructions for Array of Structures
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Solution Overview
Problem
Current processor architectures require numerous sequential load and store operations to transfer data items associated with arrays of structures (AoS) between memory and vector registers, leading to inefficiencies in high-performance computations.
Innovation Solution
The introduction of Load#N and Store#N instructions, which allow for concurrent loading and storing of multiple data items from/to multiple vector registers, reducing the number of operations needed to fully populate or empty vector registers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If sequential load and store operations are used to transfer AoS data between memory and vector registers, then data transfer can be performed using standard processor instructions, but the number of operations required increases and processing efficiency decreases
Solution Approach 1:
The patent combines multiple separate load or store operations into a single vector instruction that can simultaneously access multiple memory locations and transfer multiple data items. The vector store/load instructions are designed to operate on arrays of structures by specifying a base address and a count, enabling concurrent transfer of multiple data items associated with AoS from/to multiple vector registers in one operation, thereby reducing the total number of operations required.
2Loss of time
If multiple sequential operations are used to populate vector registers with AoS data, then compatibility with existing processor architectures is maintained, but the time required to complete data transfer increases
Solution Approach 1:
The vector store/load instructions are designed with multi-functionality to handle various data types and structures. The instructions can operate on different data element sizes (bytes, words, double-words, quad-words) and can process arrays of structures with varying numbers of elements per structure. This universal design allows a single instruction format to perform multiple functions, reducing data transfer time without requiring entirely new processor architecture.
3Device complexity
If traditional load/store instructions are used for AoS, then implementation simplicity is maintained, but the number of instructions required to transfer all data items increases
Solution Approach 1:
The patent introduces a new dimension to the traditional load/store instructions by adding vector register operands and structure element count parameters. This transforms scalar instructions that operate on single data items into vector instructions that can operate on multiple data items simultaneously. The instruction format is extended to include base address, count, and vector register specifications, enabling parallel data transfer operations that increase productivity while maintaining reasonable implementation complexity through systematic extension of existing instruction formats.
Data Source
AI summary
A processor comprises a plurality of vector registers, and an execution unit, operatively coupled to the plurality of vector registers, the execution unit comprising a logic circuit implementing a load instruction for loading, into two or more vector registers, two or more data items associated with a data structure stored in a memory, wherein each one of the two or more vector registers is to store a data item associated with a certain position number within the data structure.